$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Structures and methods to enhance copper metallization 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0196078 (2002-07-16)
발명자 / 주소
  • Farrar, Paul A.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 12  인용 특허 : 143

초록

Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator inc

대표청구항

1. A method for forming a semiconductor structure, the method comprising: forming a protective layer that comprises an insulator nitride compound; forming a first insulator layer abutting the protective layer; forming at least one opening through the protective layer and the first insulator

이 특허에 인용된 특허 (143)

  1. Bruni Marie-Dominique,FRX, Anode for a flat display screen.
  2. Xu Zheng ; Forster John ; Yao Tse-Yong, Apparatus for filling apertures in a film layer on a semiconductor substrate.
  3. Singhvi Shri ; Rengarajan Suraj ; Ding Peijun ; Yao Gongda, Barrier applications for aluminum planarization.
  4. Hichem M'Saad ; Seon Mee Cho ; Dana Tribula, Barrier layer deposition using HDP-CVD.
  5. Reynolds Glyn J. ; Hillman Joseph T., Buffer chamber for integrating physical and chemical vapor deposition chambers together in a processing system.
  6. Lu Jiong Ping ; Hwang Ming ; Anderson Dirk N. ; Kittl Jorge A. ; Tsai Hun-Lian, CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes.
  7. Farkas Janos ; Bajaj Rajeev ; Freeman Melissa ; Watts David K. ; Das Sanjit, Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers.
  8. Uzoh Cyprian E., Continuous highly conductive metal wiring structures and method for fabricating the same.
  9. Harper James M. E. (Yorktown Heights NY) Holloway Karen L. (Mount Kisco NY) Kwok Thomas Y. (Westwood NJ), Copper alloy metallurgies for VLSI interconnection structures.
  10. Harper James M. E. (Yorktown Heights NY) Holloway Karen L. (Mount Kisco NY) Kwok Thomas Y. (Westwood NJ), Copper alloy metallurgies for VLSI interconnection structures.
  11. Douglas Monte A. (Coppell TX), Copper dry etch process using organic and amine radicals.
  12. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
  13. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
  14. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
  15. Farrar Paul A., Copper metallurgy in integrated circuits.
  16. Zheng Bo ; Chen Ling ; Mak Alfred ; Chang Mei, Deposition of copper with increased adhesion.
  17. Chen Liang-Yuh ; Tao Rong ; Guo Ted ; Mosely Roderick Craig, Dual damascene metallization.
  18. Chen Liang-Yuh ; Tao Rong ; Guo Ted ; Mosely Roderick Craig, Dual damascene metallization.
  19. Wetzel Jeffrey Thomas, Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation.
  20. Klein, Rita J., Electroless deposition of doped noble metals and noble metal alloys.
  21. Shacham-Diamand Yosi ; Nguyen Vinh ; Dubin Valery, Electroless deposition of metal films with spray processor.
  22. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Electroless gold plating method for forming inductor structures.
  23. Alexander S. Kozlov ; Thirumalai Palanisamy ; Dave Narasimhan, Electroless silver plating.
  24. Nguyen Tue ; Charneski Lawrence J. ; Kobayashi Masato,JPX, Enhanced CVD copper adhesion by two-step deposition process.
  25. Tetsuo Matsuda JP; Hisashi Kaneko JP, Film formation method.
  26. Qing Tan ; Stanley Craig Beddingfield ; Douglas G. Mitchell, Fine pitch bumping with improved device standoff and bump volume.
  27. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
  28. Joshi Rajiv Vasant ; Tejwani Manu Jamnadas ; Srikrishnan Kris Venkatraman, High aspect ratio low resistivity lines/vias by surface diffusion.
  29. Jin Shu ; Mu Xiao Chun ; Chen Xing ; Bourget Lawrence, High density plasma physical vapor deposition.
  30. Farnworth Warren M. ; Akram Salman, IC contacts with palladium layer and flexible conductive epoxy bumps.
  31. Allen Gregory Lee (Vancouver WA), Implantation of nucleating species for selective metallization and products thereof.
  32. Ting Chiu H. ; Holtkamp William H., Integrated vacuum and plating cluster system.
  33. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  34. Nakano Tadashi (Chiba JPX) Ono Hideaki (Chiba JPX), Interconnection structure for semiconductor integrated circuit and manufacture of the same.
  35. Sachdev Krishna Gandhi ; Hummel John Patrick ; Kamath Sundar Mangalore ; Lang Robert Neal ; Nendaic Anton ; Perry Charles Hampton ; Sachdev Harbans, Low TCE polyimides as improved insulator in multilayer interconnect structures.
  36. Kapoor Ashok K. (Palo Alto CA) Pasch Nicholas F. (Pacifica CA), Low dielectric constant insulation layer for integrated circuit structure and method of making same.
  37. Kwon Dong-chul,KRX ; Wee Young-Jin,KRX, Low resistance interconnect for a semiconductor device and method of fabricating the same.
  38. Shan Ende ; Lau Gorley ; Geha Sam, Low temperature metallization process.
  39. Keyser Thomas (Palm Bay FL) Cairns Bruce R. (Los Altos Hills CA) Anand Kranti V. (Sunnyvale CA) Petro William G. (Cupertino CA) Barry Michael L. (Palo Alto CA), Low temperature plasma nitridation process and applications of nitride films formed thereby.
  40. Brors Daniel L. (Los Altos Hills CA) Fair James A. (Mountain View CA) Monnig Kenneth A. (Palo Alto CA), Method and apparatus for deposition of tungsten silicides.
  41. Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
  42. Farrar Paul A., Method and support structure for air bridge wiring of an integrated circuit.
  43. Omstead Thomas R. ; Wongsenakhum Panya ; Messner William J. ; Nagy Edward J. ; Starks William ; Moslehi Mehrdad M., Method and system for dispensing process gas for fabricating a device on a substrate.
  44. Filipiak Stanley M. (Pflugerville TX) Gelatos Avgerinos (Austin TX), Method for capping copper in semiconductor devices.
  45. Zhou Mei Sheng,SGX ; Ron-Fu Chu,SGX, Method for chemical-mechanical polish (CMP) planarizing of cooper containing conductor layers.
  46. Svendsen Leo Gulvad (Redwood City CA) Walker Clifford James (Fremont CA) Lykins ; II James Leborn (San Jose CA), Method for electroplating a substrate containing an electroplateable pattern.
  47. Cherng Meng-Jaw,TWX ; Li Pei-Wen,TWX, Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices.
  48. Dubin Valery ; Ting Chiu, Method for fabricating copper-aluminum metallization.
  49. Mikagi Kaoru (Tokyo JPX), Method for fabricating semiconductor device with interconnections buried in trenches.
  50. Sandhu Gurtej Sandhu (Boise ID) Yu Chris Chang (Aurora IL), Method for forming a metallization layer.
  51. Sundarrajan Arvind ; Saigal Dinesh, Method for forming a multilayered aluminum-comprising structure on a substrate.
  52. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
  53. Cooper Kent J. (Austin TX) Lin Jung-Hui (Austin TX) Roth Scott S. (Austin TX) Roman Bernard J. (Austin TX) Mazure Carlos A. (Austin TX) Nguyen Bich-Yen (Austin TX) Ray Wayne J. (Austin TX), Method for forming contact to a semiconductor device.
  54. Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
  55. Geusic Joseph E. ; Forbes Leonard ; Ahn Kie Y., Method for forming high capacitance memory cells.
  56. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
  57. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  58. Fitzsimmons John A. (Poughkeepsie NY) Havas Janos (Hopewell Junction NY) Lawson Margaret J. (Newburgh NY) Leonard Edward J. (Fishkill NY) Rhoads Bryan N. (Pine Bush NY), Method for forming patterned films on a substrate.
  59. Tsunogae Yasuo (Kawasaki JPX) Mizuno Hideharu (Kawasaki JPX) Kohara Teiji (Kawasaki JPX) Natsuume Tadao (Yokosuka JPX), Method for hydrogenation of metathesis polymers.
  60. Barton Carlos L. (Brooklyn CT) McGraw Robert B. (Westport CT), Method for metallizing fluoropolymer substrates.
  61. Jain Ajay, Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer.
  62. Chakravorty Kishore K. (Issaquah WA) Tanielian Minas H. (Bellevue WA), Method for producing a planar surface on which a conductive layer can be applied.
  63. Fiordalice Robert ; Garcia Sam ; Ong T. P., Method of decreasing resistivity in an electrically conductive layer.
  64. Nogami Takeshi ; Dubin Valery ; Cheung Robin, Method of electroplating a copper or copper alloy interconnect.
  65. van Laarhoven Josephus M. F. G. (Eindhoven NLX) de Bruin Leendert (Eindhoven NLX) van Arendonk Anton P. M. (Eindhoven NLX), Method of enabling electrical connection to a substructure forming part of an electronic device.
  66. Paul A. Farrar, Method of fabricating a barrier layer associated with a conductor layer in damascene structures.
  67. Jing-Cheng Lin TW; Shau-Lin Shue TW; Chen-Hua Yu TW, Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process.
  68. Ahn Kie Y., Method of fabricating integrated circuit wiring with low RC time delay.
  69. Hsu Chen-Chung,TWX ; Chang Yih-Jau,TWX, Method of fabricating semiconductor device for preventing antenna effect.
  70. Mikagi Kaoru,JPX, Method of fabricating semiconductor device providing effective resistance against metal layer oxidation and diffusion.
  71. Wada Junichi,JPX ; Sakata Atsuko,JPX ; Katata Tomio,JPX ; Usui Takamasa,JPX ; Hasunuma Masahiko,JPX ; Shibata Hideki,JPX ; Kaneko Hisashi,JPX ; Hayasaka Nobuo,JPX ; Okumura Katsuya,JPX, Method of filling contact holes and wiring grooves of a semiconductor device.
  72. Ong Edith (Saratoga CA), Method of filling contacts in semiconductor devices.
  73. Gilton Terry L. ; Chopra Dinesh, Method of forming a metal seed layer for subsequent plating.
  74. Farrar Paul A., Method of forming a support structure for air bridge wiring of an integrated circuit.
  75. Venkatraman Ramnath ; Weitzman Elizabeth J. ; Fiordalice Robert W., Method of forming an interconnect structure.
  76. Chien Rong-Wu,TWX ; Yen Tzu-Shih,TWX, Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers.
  77. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
  78. Hong Qi-Zhong ; Jeng Shin-Puu ; Hsu Wei-Yung, Method of forming diffusion barriers encapsulating copper.
  79. Farrar Paul A., Method of forming foamed polymeric material for an integrated circuit.
  80. Choi Kyeong Keun (Ichonkun KRX), Method of forming metal interconnection layer of semiconductor device.
  81. Buynoski Matthew S. ; Lin Ming-Ren, Method of forming multiple levels of patterned metallization.
  82. Beinglass Israel ; Srinivas Ramanujapuram A., Method of making polysilicon/tungsten silicide multilayer composite on an integrated circuit structure.
  83. Numata Ken (Dallas TX), Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layer.
  84. Suehiro Shintaro,JPX ; Akasaka Yasushi,JPX ; Suguro Kyoichi,JPX ; Nakajima Kazuaki,JPX ; Iijima Tadashi,JPX, Method of manufacturing a semiconductor device.
  85. Nakasaki Yasushi (Yokohama JPX), Method of manufacturing a semiconductor device with a copper wiring layer.
  86. Iwasaki Haruo,JPX, Method of producing cylindrical storage node of stacked capacitor in memory cell.
  87. Canaperi Donald F. (Bridgewater CT) Jagannathan Rangarajan (Patterson NY) Krishnan Mahadevaiyer (Hopewell Junction NY), Method of replenishing electroless gold plating baths.
  88. Doan Trung T. (Boise ID) Tuttle Mark E. (Boise ID), Method to form a low resistant bond pad interconnect.
  89. Uzoh Cyprian Emeka ; Greco Stephen Edward, Method to selectively fill recesses with conductive metal.
  90. Kie Y. Ahn ; Leonard Forbes, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  91. Ahn Kie Y. ; Forbes Leonard, Methods for making copper and other metal interconnections in integrated circuits.
  92. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.
  93. Carey David H. (Austin TX), Methods of forming channels and vias in insulating layers.
  94. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  95. Schmitt ; III Jerome J. (New Haven CT) Halpern Bret L. (Bethany CT), Microwave plasma assisted supersonic gas jet deposition of thin film materials.
  96. Morishita Yasuyuki (Tokyo JPX), Multi-layer wiring structure in semiconductor device and method for manufacturing the same.
  97. Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers.
  98. Hautala John J. ; Westendorp Johannes F. M., PECVD of TaN films from tantalum halide precursors.
  99. Chow Yu C. (Irvine CA) Liao Kuan-Yang (Irvine CA) Chin Maw-Rong (Huntington Beach CA), Plasma-nitridated self-aligned tungsten system for VLSI interconnections.
  100. Ting Chiu ; Dubin Valery, Plated copper interconnect structure.
  101. Havemann Robert H. ; Stoltz Richard A., Process for conductors with selective deposition.
  102. Misawa Nobuhiro (Kawasaki JPX), Process for fabricating integrated circuit devices.
  103. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
  104. Jain Ajay, Process for forming a semiconductor device.
  105. Tobin Philip J. ; Hegde Rama I. ; Tseng Hsing-Huang ; O'Meara David ; Wang Victor, Process for forming a semiconductor device.
  106. Zhang Jiming ; Denning Dean J., Process for forming a semiconductor device.
  107. Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY), Process for making multilayer integrated circuit substrate.
  108. Tokunaga Takafumi (Tokorozawa JPX) Tsuneoka Masatoshi (Ohme JPX) Mizukami Koichiro (Akishima JPX), Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device.
  109. Paul A. Farrar, Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy.
  110. Awaya Nobuyoshi (Isehara JPX) Arita Yoshinobu (Isehara JPX), Process for selectively growing thin metallic film of copper or gold.
  111. Ping-Chuan Wang ; Ronald G. Filippi ; Robert D. Edwards ; Edward W. Kiewra ; Roy C. Iggulden, Process of enclosing via for improved reliability in dual damascene interconnects.
  112. Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and h.
  113. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  114. Hsu Wei-Yung ; Hong Qi-Zhong, Reduced temperature contact/via filling.
  115. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  116. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
  117. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
  118. Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
  119. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  120. Dennison Charles H. ; Doan Trung T., Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein.
  121. Blalock Guy T. ; Howard Bradley J., Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures.
  122. Clampitt Darwin A., Semiconductor circuit interconnections and methods of making such interconnections.
  123. IIjima Tadashi,JPX ; Ono Hisako,JPX ; Ushiku Yukihiro,JPX ; Nishiyama Akira,NLX ; Nakasa Naomi,JPX, Semiconductor device and method of manufacturing the same.
  124. Hughes Henry G. (Scottsdale AZ) Lue Ping-Chang (Scottsdale AZ) Robinson Frederick J. (Scottsdale AZ), Semiconductor device having a low permittivity dielectric.
  125. Xu Zheng ; Forster John ; Yao Tse-Yong, Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches.
  126. Tsukune Atsuhiro (Kawasaki JPX) Suzuki Kiyokatsu (Kawasaki JPX) Matsuura Katsuyoshi (Kawasaki JPX) Mieno Fumitake (Kawasaki JPX) Yamanishi Hirokazu (Kawasaki JPX), Semiconductor device manufacturing apparatus and its cleaning method.
  127. Suehiro Shintaro,JPX ; Akasaka Yasushi,JPX ; Suguro Kyoichi,JPX ; Nakajima Kazuaki,JPX ; Iijima Tadashi,JPX, Semiconductor device wiring or electrode.
  128. Tomita, Kenichi; Inoue, Tomotoshi; Terada, Toshiyuki, Semiconductor integrated circuit device having a hollow multi-layered lead structure.
  129. Shirk Albert (Palmyra PA) Ceresa Myron (Advance NC), Sensitized polyimides and circuit elements thereof.
  130. Chittipeddi Sailesh ; Merchant Sailesh Mansinh, Silicon IC contacts using composite TiN barrier layer.
  131. Yao Gongda ; Ding Peijun ; Xu Zheng ; Kieu Hoa, Silicon-doped titanium wetting layer for aluminum plug.
  132. 8437 ; 19920400 ; Kenna, Site-selective electrochemical deposition of copper.
  133. Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Sputter deposited barrier layers.
  134. Chiang Tony ; Ding Peijun ; Chin Barry L., Sputtering methods for depositing stress tunable tantalum and tantalum nitride films.
  135. Paul A. Farrar, Structures and methods to enhance copper metallization.
  136. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
  137. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  138. Kholodenko Arnold ; Lee Ke Ling ; Shendon Maya ; Quiles Efrain, Temperature control system for semiconductor process chamber.
  139. Young Peter L. (South Barrington IL) Cech Jay (Elmhurst IL) Li Kin (Lombard IL), Thin-film electrical connections for integrated circuits.
  140. Hall R. Dean (Baltimore MD), Tin and gold plating process.
  141. Sandhu Gurtej S. (Boise ID), Tungsten silicide (WSix) deposition process for semiconductor manufacture.
  142. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
  143. Farnworth Warren M. ; Akram Salman, Use of palladium in IC manufacturing.

이 특허를 인용한 특허 (12)

  1. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.
  2. Farrar,Paul A., Hplasma treatment.
  3. Farrar, Paul A., Integrated circuit and seed layers.
  4. Farrar,Paul A., Integrated circuit and seed layers.
  5. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  6. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  7. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  8. Farrar, Paul A., Structures and methods to enhance copper metallization.
  9. Farrar, Paul A., Structures and methods to enhance copper metallization.
  10. Farrar,Paul A., Structures and methods to enhance copper metallization.
  11. Farrar,Paul A., Structures and methods to enhance copper metallization.
  12. Yang, Chih-Chao; Edelstein, Daniel C., Tungsten metallization: structure and fabrication of same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로