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A multichip semiconductor package device includes first and second devices and a conductive bond. The first device includes an insulative housing, a first semiconductor chip and a conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relati

A multichip semiconductor package device includes first and second devices and a conductive bond. The first device includes an insulative housing, a first semiconductor chip and a conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity. The conductive trace includes a terminal that extends through the central portion and a lead that protrudes laterally from and extends through the side surface. The second device includes a second semiconductor chip, extends into the cavity and is positioned within and does not extend outside a periphery of the cavity. The conductive bond is inside the cavity, on the terminal and contacts and electrically connects the first and second devices.

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1. A multichip semiconductor package device, comprising: a first device that includes: an insulative housing with a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, wherein the bottom surface includes a peripheral ledge and a central portion that i

1. A multichip semiconductor package device, comprising: a first device that includes: an insulative housing with a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, wherein the bottom surface includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity;a first semiconductor chip within the insulative housing and outside the cavity, wherein the first chip includes an upper surface and a lower surface, and the upper surface includes a conductive pad; anda conductive trace that includes a terminal and a lead, wherein the terminal extends through the central portion, the lead protrudes laterally from and extends through the side surface, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another and to the pad; a second device that includes a second semiconductor chip, wherein the second device extends into the cavity and is positioned within and does not extend outside a periphery of the cavity; and a conductive bond inside the cavity and on the terminal that contacts and electrically connects the first and second devices. 2. The multichip device of claim 1, wherein the insulative housing includes a first single-piece housing portion that contacts the lead and is spaced from the terminal and a second single-piece housing portion that contacts the first single-piece housing portion and the terminal.3. The multichip device of claim 2, wherein the first single-piece housing portion provides the top surface, the side surface and the peripheral ledge, and the second single-piece housing portion provides the central portion.4. The multichip device of claim 3, wherein the first single-piece housing portion contacts the lower surface.5. The multichip device of claim 3, wherein the insulative housing consists of the first and second single-piece housing portions.6. The multichip device of claim 1, wherein the terminal protrudes vertically from the central portion into the cavity.7. The multichip device of claim 1, wherein the terminal is aligned with the central portion.8. The multichip device of claim 1, wherein the terminal is within a periphery of the first chip.9. The multichip device of claim 1, wherein the terminal is within a periphery of the second chip.10. The multichip device of claim 1, wherein the first chip is within and does not extend outside the periphery of the cavity.11. The multichip device of claim 1, wherein the first device is a single-chip package.12. The multichip device of claim 1, wherein the first device is devoid of an electrical conductor that extends through the top surface.13. The multichip device of claim 1, wherein the second device contacts the peripheral ledge.14. The multichip device of claim 1, wherein the second device is spaced from the peripheral ledge.15. The multichip device of claim 1, wherein the second device occupies a majority of the cavity.16. The multichip device of claim 1, wherein the second device occupies a minority of the cavity.17. The multichip device of claim 1, wherein the second device is the second chip.18. The multichip device of claim 1, wherein the second device is a chip scale package.19. The multichip device of claim 1, wherein the first device is a TSOP package, and the second device is a chip scale package.20. The multichip device of claim 1, wherein the multichip device is devoid of wire bonds and TAB leads.21. A multichip semiconductor package device, comprising: a first device that includes: an insulative housing with a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, wherein the bottom surface includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a ca vity;a first semiconductor chip within the insulative housing and outside the cavity, wherein the first chip includes a upper surface and a lower surface, the upper surface includes a conductive pad, the upper surface faces towards the bottom surface and faces away from the top surface, and the insulative housing contacts the lower surface; anda conductive trace that includes a terminal and a lead, wherein the terminal extends through the central portion, the lead protrudes laterally from and extends through the side surface, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another and the pad; a second device that includes a second semiconductor chip, wherein the second device extends into the cavity and is positioned within and does not extend outside a periphery of the cavity; and a conductive bond inside the cavity and on the terminal that contacts and electrically connects the first and second devices. 22. The multichip device of claim 21, wherein the insulative housing consists of first and second single-piece housing portions, the first single-piece housing portion provides the top surface, the side surface and the peripheral ledge, contacts the lower surface and the lead and is spaced from the terminal, and the second single-piece housing portion provides the central portion and contacts the first single-piece housing portion and the terminal.23. The multichip device of claim 21, wherein the terminal is within a periphery of the first chip and a periphery of the second chip.24. The multichip device of claim 21, wherein the conductive bond is within a periphery of the first chip and a periphery of the second chip.25. The multichip device of claim 21, wherein the first chip is within and does not extend outside the periphery of the cavity.26. The multichip device of claim 21, wherein the first device is a single-chip package.27. The multichip device of claim 21, wherein the second device is the second chip.28. The multichip device of claim 21, wherein the second device is a chip scale package.29. The multichip device of claim 21, wherein the first device is a TSOP package, and the second device is a chip scale package.30. The multichip device of claim 21, wherein the multichip device is devoid of wire bonds and TAB leads.31. A multichip semiconductor package device, comprising: a first device that includes: an insulative housing with a top surface, a bottom surface, and peripheral side surfaces between the top and bottom surfaces, wherein the bottom surface includes a peripheral ledge and a central portion, the peripheral ledge is integral with the side surfaces, the central portion is within the peripheral ledge, spaced from the side surfaces and recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity;a first semiconductor chip within and surrounded by the insulative housing and outside the cavity, wherein the first chip includes an upper surface and a lower surface, the upper surface includes a conductive pad, the upper surface faces towards the bottom surface and faces away from the top surface, and the insulative housing contacts the lower surface; anda conductive trace that includes a terminal and a lead, wherein the terminal extends through the central portion, the lead protrudes laterally from and extends through the side surface, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another and the pad inside the insulative housing and outside the first chip; a second device that includes a second semiconductor chip, wherein the second device includes a major surface inside the cavity, and the second device is positioned within and does not extend outside a periphery of the cavity; and a conductive bond inside the cavity and on the terminal that contacts and electrically connects the first and second devices. 32. The multichip device of claim 31, wherein the insulative housing consists of first and second single-piece housing portions, the first single-piece housing portion provides the top surface, the side surfaces and the peripheral ledge, contacts the lower surface and the lead and is spaced from the terminal, and the second single-piece housing portion provides the central portion and contacts the first single-piece housing portion and the terminal.33. The multichip device of claim 31, wherein the terminal is within a periphery of the first chip and a periphery of the second chip.34. The multichip device of claim 31, wherein the conductive bond is within a periphery of the first chip and a periphery of the second chip.35. The multichip device of claim 31, wherein the first chip is within and does not extend outside the periphery of the cavity.36. The multichip device of claim 31, wherein the first device is a single-chip package.37. The multichip device of claim 31, wherein the second device is the second chip.38. The multichip device of claim 31, wherein the second device is a chip scale package.39. The multichip device of claim 31, wherein the first device is a TSOP package, and the second device is a chip scale package.40. The multichip device of claim 31, wherein the multichip device is devoid of wire bonds and TAB leads.