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Three level direct communication connections between neighboring multiple context processing elements

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/17
출원번호 US-0364838 (1999-07-30)
발명자 / 주소
  • Mirsky, Ethan
  • French, Robert
  • Eslick, Ian
출원인 / 주소
  • Broadcom Corporation
대리인 / 주소
    Christie, Parker & Hale, LLP
인용정보 피인용 횟수 : 44  인용 특허 : 21

초록

A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each int

대표청구항

1. A method for programming and manipulating a networked array of multiple context processing elements (MCPEs), the method comprising: selectively transmitting third signals over a level 3 network, wherein the level 3 network comprises a plurality of channels between pairs of MCPEs in the networke

이 특허에 인용된 특허 (21)

  1. Mohamed Ahmed Hassan, Architecture and method for sharing TLB entries through process IDS.
  2. Deering Michael F. (Mountain View CA), Arithmetic logic system using the output of a first alu to control the operation of a second alu.
  3. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
  4. Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
  5. Garverick Tim (Cupertino CA) Camarota Rafael C. (San Jose CA), Dynamic three-state bussing capability in a configurable logic array.
  6. DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
  7. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  8. Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.
  9. Cook Peter W. (Mount Kisco NY), IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to.
  10. Pierce Kerry M. (Canby OR) Erickson Charles R. (Fremont CA) Huang Chih-Tsung (Burlingame CA) Wieland Douglas P. (Sunnyvale CA), Interconnect architecture for field programmable gate array using variable length conductors.
  11. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  12. Guyer James M. (Marlboro MA) Epstein David I. (Framingham MA) Keating David L. (Holliston MA) Anderson Walker (Arlington MA) Veres James E. (Framingham MA) Kimmens Harold R. (Hudson MA), Method and apparatus for enhancing the operation of a data processing system.
  13. Leung Wai-Bor (Wescosville PA), Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended fo.
  14. Yetter Jeffry D., Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages.
  15. Chiarulli Donald M. (4724 Newcomb Dr. Baton Rouge LA 70808) Rudd W. G. (Dept. of Computer Science Oregon State University Corvallis OR 97331) Buell Duncan A. (1212 Chippenham Dr. Baton Rouge LA 70808, Processor utilizing reconfigurable process segments to accomodate data word length.
  16. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.
  17. Ong Randy T. (Cupertino CA), Programmable logic device which stores more than one configuration and means for switching configurations.
  18. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device with hierarchical confiquration and state storage.
  19. Saccardi Raymond J. (Laurel MD), Reconfigurable pipelined processor.
  20. Gorin Allen L. (Fair Lawn NJ) Makofsky Patrick A. (Randolph NJ) Morton Nancy (Dover NJ) Oliver Neal C. (Madison NJ) Shively Richard R. (Convent Station NJ) Stanziola Christopher A. (Hyde Park NY), Reconfigurable signal processor.
  21. Duong Khue, Tile-based modular routing resources for high density programmable logic device.

이 특허를 인용한 특허 (44)

  1. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
  2. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  3. Wilkinson, III,Hugh M.; Rosenbluth,Mark B.; Adiletta,Matthew J.; Bernstein,Debra; Wolrich,Gilbert, Context pipelines.
  4. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  5. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  6. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  7. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  8. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  9. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
  10. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
  11. Watt,William; Verheyen,Henry T., Hardware acceleration system for logic simulation using shift register as local cache.
  12. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
  13. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  14. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  15. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  16. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  17. Ryu, Soo jung; Kim, Jeong wook; Kim, Suk jin; Kim, Hong Seok; Kong, Jun jin, Loop accelerator and data processing system having the same.
  18. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  19. Vorbach, Martin, Method for debugging reconfigurable architectures.
  20. Vorbach, Martin, Method for debugging reconfigurable architectures.
  21. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  22. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  23. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  24. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  25. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  26. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  27. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  28. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  29. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  30. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  31. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  32. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  33. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  34. Wilkinson, III,Hugh M.; Adiletta,Matthew J.; Wolrich,Gilbert; Rosenbluth,Mark B.; Bernstein,Debra; Wilde,Myles J., Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access.
  35. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  36. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  37. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  38. Hanai, Takashi; Kawano, Tetsuo, Reconfigurable circuit.
  39. Vorbach, Martin, Reconfigurable elements.
  40. Vorbach, Martin, Reconfigurable elements.
  41. Vorbach, Martin, Reconfigurable sequencer structure.
  42. Vorbach, Martin, Reconfigurable sequencer structure.
  43. Vorbach, Martin; Bretz, Daniel, Router.
  44. Mitu, Bogdan; Bivolarksi, Lazar; Stefan, Gheorghe, System and method for class-based execution of an instruction broadcasted to an array of processing elements.
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