초록 ▼

A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysili

A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysilicon line sidewalls are no longer covered with spacer oxide but all silicide pre-cleans can clear the poly sidewalls completely which thus leads to improved silicidation conditions, resulting in gate lines exhibiting very low sheet resistivity.

대표청구항 ▼

1. A method, comprising: forming at least one feature of a silicon-containing semiconductive material on a substrate, said feature having sidewalls and an upper surface; forming a dielectric layer on said sidewalls of said at least one feature, said dielectric layer covering portions of said su

1. A method, comprising: forming at least one feature of a silicon-containing semiconductive material on a substrate, said feature having sidewalls and an upper surface; forming a dielectric layer on said sidewalls of said at least one feature, said dielectric layer covering portions of said substrate adjacent said sidewalls; introducing dopant material into at least the portions of said substrate not covered by said feature and said dielectric layer on said sidewalls; removing said dielectric layer so as to expose the sidewalls of said feature; and forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming said spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one feature and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one feature are exposed. 2. The method of claim 1, wherein forming said dielectric layer comprises forming said dielectric layer on at least the upper surface and the sidewalls of said at least one feature and anisotropically etching said dielectric layer so as to expose at least the upper surface of said at least one feature.3. The method of claim 2, wherein said dielectric layer comprises at least one of silicon nitride and silicon oxide.4. The method of claim 1, wherein introducing dopant material comprises implanting said dopant material at a predefined concentration and diffusing said dopant material during a thermal treatment.5. The method of claim 1, wherein removing said dielectric layer comprises performing at least one of a dry etching and a wet etching process on said dielectric layer.6. The method of claim 1, further comprising forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one feature.7. The method of claim 6, wherein forming a metal silicide layer comprises depositing at least one metal layer on at least the upper surface and the exposed upper sidewall portions of said at least one feature and reacting at least partially said metal into metal silicide by a thermal treatment.8. The method of claim 7, further comprising removing unreacted metal after the thermal treatment by selective wet etching.9. A method of forming a gate electrode, the method comprising: forming at least one polysilicon line above an active region of a substrate; introducing a first dopant material into at least one portion of said active region not covered by said at least one polysilicon line and into said at least one polysilicon line; forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said active region adjacent to said sidewalls; introducing a second dopant material into at least the portions of the active region not covered by said polysilicon line and said dielectric layer, wherein introducing said second dopant material comprises implanting said second dopant material at a second predefined concentration and diffusing said dopant material during a second thermal treatment; removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line; and forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions. 10. The method of claim 9, wherein forming said dielectric layer comprises forming a dielectric layer on at least the upper surface of said at least one polysilicon line and anisotropically etching said dielectric layer so as to expose at least the upper surface of said at least one polysilicon line .11. The method of claim 10, wherein, said dielectric layer comprises at least one of silicon nitride, silicon oxide and a combination thereof.12. The method of claim 9, wherein introducing said first dopant material comprises implanting said first dopant material at a first predefined concentration and diffusing said first dopant material during a first thermal treatment.13. The method of claim 9, wherein removing said dielectric layer comprises performing at least one of a dry etching and a wet etching process on said dielectric layer.14. The method of claim 9, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed.15. The method of claim 9, further comprising forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line.16. The method of claim 15, wherein forming said metal silicide layer comprises depositing at least one metal layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line and reacting at least partially said metal into metal silicide by a thermal treatment.17. The method of claim 16, further comprising removing unreacted metal after the thermal treatment by selective wet etching.18. A method, comprising: forming at least one polysilicon line above a substrate; introducing a first dopant material at a first predefined concentration into at least one portion of said substrate not covered by said at least one polysilicon line and into said at least one polysilicon line; forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said substrate adjacent to said sidewalls; introducing a second dopant material at a second predefined concentration higher than said first concentration into at least the portions of the substrate not covered by said polysilicon line and said dielectric layer, wherein introducing said second dopant material comprises implanting said dopant material at said second predefined concentration and diffusing said second dopant material during a second thermal treatment; removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line; forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions; and forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line. 19. The method of claim 18, wherein forming said dielectric layer comprises forming a dielectric layer on at least the upper surface and the sidewalls of said at least one polysilicon line and anisotropically etching said dielectric layer so as to expose at least the upper surface of said at least one polysilicon line.20. The method of claim 19, wherein said dielectric layer comprises at least one of silicon nitride, silicon oxide and a combination thereof.21. The method of claim 18, wherein introducing said first dopant material comprises implanting said first dopant material at said first predefined concentration and diffusing said first dopant material during a first thermal treatment.22. The method of claim 18, wherein removing said dielectric layer comprises performing at least one of a dry etching and a wet etching process on said dielectric layer.23. The method of claim 18, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper s urface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed.24. The method of claim 18, wherein forming a metal silicide layer comprises depositing at least one metal layer on said substrate and reacting at least partially said metal into metal silicide by a thermal treatment at the polysilicon-metal and silicon-metal interfaces.25. The method of claim 24, further comprising removing unreacted metal after the thermal treatment by selective wet etching.26. A method, comprising: forming at least one polysilicon line above a substrate; introducing a first dopant material at a first predefined concentration into at least one portion of said substrate not covered by said at least one polysilicon line and into said at least one polysilicon line; forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said substrate adjacent to said sidewalls; introducing a second dopant material at a second predefined concentration lower than said first concentration into at least the portions of the substrate not covered by said polysilicon line and said dielectric layer, wherein introducing said second dopant material comprises implanting said second dopant material at said second predefined concentration and diffusing said dopant material during a second thermal treatment; removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line; forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions; and forming a metal suicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line. 27. The method of claim 26, wherein forming said dielectric layer comprises forming said dielectric layer on at least the upper surface and the sidewalls of said at least one polysilicon line and anisotropically etching said dielectric layer so as to expose at least the upper surface of said at least one polysilicon line.28. The method of claim 27, wherein said dielectric layer comprises at least one of silicon nitride, silicon oxide and a combination thereof.29. The method of claim 26, wherein introducing said first dopant material comprises implanting said first dopant material at said first predefined concentration and diffusing said first dopant material during a first thermal treatment.30. The method of claim 26, wherein removing said dielectric layer comprises performing at least one of a dry etching and a wet etching process on said dielectric layer.31. The method of claim 26, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed.32. The method of claim 26, wherein forming a metal silicide layer comprises depositing at least one metal layer on said substrate and reacting at least partially said metal into metal silicide by a thermal treatment at the polysilicon-metal and silicon-metal interfaces.33. The method of claim 32, further comprising removing unreacted metal after the thermal treatment by selective wet etching.34. A method of forming a gate electrode, the method comprising: forming at least one polysilicon line above an active region of a substrate; introducing a first dopant material into at lea st one portion of said active region not covered by said at least one polysilicon line and into said at least one polysilicon line; forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said active region adjacent to said sidewalls; introducing a second dopant material into at least the portions of the active region not covered by said polysilicon line and said dielectric layer; removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line; and forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed. 35. A method, comprising: forming at least one polysilicon line above a substrate; introducing a fist dopant material at a first predefined concentration into at least one portion of said substrate not covered by said at least one polysilicon line and into said at least one polysilicon line; forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said substrate adjacent to said sidewalls; introducing a second dopant material at a second predefined concentration higher than said first concentration into at least the portions of the substrate not covered by said polysilicon line and said dielectric layer; removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line; forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed; and forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line. 36. A method, comprising: forming at least one polysilicon line above a substrate; introducing a first dopant material at a first predefined concentration into at least one portion of said substrate not covered by said at least one polysilicon line and into said at least one polysilicon line; forming a dielectric layer on the sidewalls of said at least one polysilicon line, said dielectric layer covering portions of said substrate adjacent to said sidewalls; introducing a second dopant material at a second predefined concentration lower than said first concentration into at least the portions of the substrate not covered by said polysilicon line and said dielectric layer; removing said dielectric layer so as to expose the sidewalls of said at least one polysilicon line; forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one polysilicon line and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one polysilicon line are exposed; and forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of said at least one polysilicon line.