$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method and apparatus for reducing power consumption 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/26
출원번호 US-0670041 (2000-09-26)
발명자 / 주소
  • Mirov, Russell N.
  • Cekleov, Michel
  • Young, Mark
  • Baldwin, William M.
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Meyertons Hood Kivlin Kowert & Goetzel, P.C.
인용정보 피인용 횟수 : 139  인용 특허 : 12

초록

A method for controlling thermal cycles in a computer system is provided. The method is comprised of receiving a request to transition the computer system from a first operating mode to a second operating mode, where less power is consumed in the second operating mode. A historical rate at which the

대표청구항

1. A method for controlling thermal cycles in a computer system, comprising: receiving a request to transition the computer system from a first operating mode to a second operating mode, where the first and second operating modes consume differing amounts of power; determining a historical rate

이 특허에 인용된 특허 (12)

  1. Holst John Christian ; Draper Donald A., Active power supply filter.
  2. Ho Kenneth S., Apparatus and method for switching frequency modes in a phase locked loop system.
  3. Rogers Alan C. (Palo Alto CA), High reliability phase-locked loop.
  4. Whatley Terry ; Nowshadi Saeed ; Linden Peter van der ; Gianni Robert R. ; Melanson Ron, Method and apparatus for selectively inhibiting power shutdowns based upon the number of power shutdowns that an electr.
  5. Hirst B. Mark, Multiple frequency switching power supply and methods to operate a switching power supply.
  6. Rogers Alan C., PLL system clock generator with instantaneous clock frequency shifting.
  7. Shigemori Mikio ; Karasawa Hideo,JPX ; Kano Toshihiko,JPX ; Ichinose Kazushige,JPX, Phase locked loop clock source provided with a plurality of frequency adjustments.
  8. Molloy Nicholas J. (Haverhill MA), Phase locked loop including non-integer multiple frequency reference signal.
  9. Aulet Nancy Ruth ; Beers Gregory Edward, Phase-locked loop circuit with dynamic backup.
  10. Ikeda Osamu (Tokyo JPX), Power saving control system for computer system.
  11. Barnes Cooper, System and method for managing a plurality of processor performance states.
  12. Barnes Cooper, Thermal control within systems having multiple CPU performance states.

이 특허를 인용한 특허 (139)

  1. C. R., Sunil Kumar; Kumar, Aruna; Radhakrishnan, Prakash K., Adapting operating parameters of an input/output (IO) interface circuit of a processor.
  2. Ignowski, James S.; Bace, Matthew M.; Dehaemer, Eric J.; Poirier, Chris, Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states.
  3. Varma, Ankush; Steiner, Ian; Ananthakrishnan, Avinash; Sistla, Krishnakanth; Poirier, Chris; Bace, Matthew; Dehaemer, Eric, Adaptively limiting a maximum operating frequency in a multicore processor.
  4. Thomas, Tessil; Kandula, Phani Kumar; Krithivas, Ramamurthy; Chin, Howard; Steiner, Ian M.; Garg, Vivek, Apparatus and method for thermal management in a multi-chip package.
  5. Conrad, Shaun M.; Gunther, Stephen H., Apparatus and method to manage energy usage of a processor.
  6. Wang, Zhiguo; Ayers, David J.; Balasubramanian, Srikanth; Gupta, Sukirti; Rusu, Stefan; Ramey, Stephen M., Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores.
  7. Cherukuri, John R.; Ahmed, Ak R.; Subbiah, Arun; Damaraju, Satish, Circuit technique to reduce leakage during reduced power mode.
  8. Bhandaru, Malini K.; Dehaemer, Eric J.; Bobholz, Scott P.; Makaram, Raghunandan; Garg, Vivek, Configuring power management functionality in a processor.
  9. Bhandaru, Malini K.; Dehaemer, Eric J.; Bobholz, Scott P.; Makaram, Raghunandan; Garg, Vivek, Configuring power management functionality in a processor.
  10. Bhandaru, Malini K.; Dehaemer, Eric J.; Bobholz, Scott P.; Makaram, Raghunandan; Garg, Vivek, Configuring power management functionality in a processor.
  11. Bhandaru, Malini K.; Dehaemer, Eric J.; Bobholz, Scott P.; Makaram, Raghunandan; Garg, Vivek, Configuring power management functionality in a processor.
  12. Bhandaru, Malini K.; Dehaemer, Eric J.; Bobholz, Scott P.; Makaram, Raghunandan; Garg, Vivek, Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator.
  13. Ananthakrishnan, Avinash N.; Gunther, Stephen H.; Shrall, Jeremy J., Constraining processor operation based on power envelope information.
  14. Weissmann, Eliezer; Abu Salah, Hisham; Rotem, Efraim; Therien, Guy M.; Shulman, Nadav; Natanzon, Esfir; Diefenbaugh, Paul S., Controlling a guaranteed frequency of a processor.
  15. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Weissmann, Eliezer; Wells, Ryan; Shulman, Nadav, Controlling a turbo mode frequency of a processor.
  16. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Weissmann, Eliezer; Wells, Ryan; Shulman, Nadav, Controlling a turbo mode frequency of a processor.
  17. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Wiessman, Eliezer; Wells, Ryan; Shulman, Nadav, Controlling a turbo mode frequency of a processor.
  18. Shrall, Jeremy J.; Gunther, Stephen H.; Sistla, Krishnakanth V.; Wells, Ryan D.; Conrad, Shaun M., Controlling configurable peak performance limits of a processor.
  19. Shrall, Jeremy J.; Gunther, Stephen H.; Sistla, Krishnakanth V.; Wells, Ryan D.; Conrad, Shaun M., Controlling configurable peak performance limits of a processor.
  20. Shrall, Jeremy J.; Gunther, Stephen H.; Sistla, Krishnakanth V.; Wells, Ryan D.; Conrad, Shaun M., Controlling configurable peak performance limits of a processor.
  21. Ananthakrishnan, Avinash N.; Rodriguez, Jorge P., Controlling current consumption of a processor based at least in part on platform capacitance.
  22. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Shrall, Jeremy J.; Samson, Eric C.; Weissmann, Eliezer; Wells, Ryan, Controlling operating frequency of a core domain based on operating condition of a non-core domain of a multi-domain processor.
  23. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Shrall, Jeremy J.; Samson, Eric C.; Weissmann, Eliezer; Wells, Ryan, Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor.
  24. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Shrall, Jeremy J.; Samson, Eric C.; Wiessmann, Eliezer; Wells, Ryan, Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor.
  25. Wells, Ryan D.; Feit, Itai; Rajwan, Doron; Shulman, Nadav; Offen, Zeev; Sodhi, Inder M., Controlling operating voltage of a processor.
  26. Wells, Ryan D.; Feit, Itai; Rajwan, Doron; Shulman, Nadav; Offen, Zeev; Sodhi, Inder M., Controlling operating voltage of a processor.
  27. Weissmann, Eliezer; Rotem, Efraim; Abu Salah, Hisham; Aizik, Yoni; Rajwan, Doron; Rosenzweig, Nir; Leibovich, Gal; Sabin, Yevgeni; Levy, Shay, Controlling performance states of processing engines of a processor.
  28. Jahagirdar, Sanjeev S.; Damaraju, Satish K.; Chen, Yun-Han; Wells, Ryan D.; Sodhi, Inder M.; Sarurkar, Vishram; Drottar, Ken; Choubal, Ashish V.; Islam, Rabiul, Controlling power delivery to a processor via a bypass.
  29. Jahagirdar, Sanjeev S.; Damaraju, Satish K.; Chen, Yun-Han; Wells, Ryan D.; Sodhi, Inder M.; Sarurkar, Vishram; Drottar, Ken; Choubal, Ashish V.; Islam, Rabiul, Controlling power delivery to a processor via a bypass.
  30. Lim, Ghim Boon, Controlling processor performance scaling based on context.
  31. Lim, Ghim Boon, Controlling processor performance scaling based on context.
  32. Garg, Vivek; Gendler, Alexander; Raman, Arvind; Choubal, Ashish V.; Sistla, Krishnakanth V.; Mulla, Dean; Dehaemer, Eric J.; Agrawal, Rahul; Sotomayor, Guy G., Controlling telemetry data communication in a processor.
  33. Rangarajan, Thanunathan; Risbud, Vinayak P.; Yasmin, Tabassum, Controlling temperature of a system memory.
  34. Rangarajan, Thanunathan; Risbud, Vinayak P.; Yasmin, Tabassum, Controlling temperature of a system memory.
  35. Ananthakrishan, Avinash N.; Ziv, Tomer; Rajwan, Doron; Rotem, Efraim, Controlling temperature of multiple domains of a multi-domain processor using a cross domain margin.
  36. Ananthakrishnan, Avinash N.; Ziv, Tomer; Rajwan, Doron; Rotem, Efraim, Controlling temperature of multiple domains of a multi-domain processor using a cross-domain margin.
  37. Kumar, Anil K., Controlling turbo mode frequency operation in a processor.
  38. Schluessler, Travis T.; Wells, Ryan D.; Romano, Yaakov, Distributing power to heterogeneous compute elements of a processor.
  39. Schluessler, Travis T.; Wells, Ryan D.; Romano, Yaakov, Distributing power to heterogeneous compute elements of a processor.
  40. Ganpule, Tapan A.; Sodhi, Inder M.; Talker, Yair; Falkov, Inbar; Khondker, Tanveer R., Dyanamically adapting a voltage of a clock generation circuit.
  41. Ganpule, Tapan A.; Sodhi, Inder M.; Talker, Yair; Falkov, Inbar; Khondker, Tanveer R., Dyanamically adapting a voltage of a clock generation circuit.
  42. Shrall, Jeremy J.; Schwartz, Jay D.; Gunther, Stephen H., Dynamic balancing of power across a plurality of processor domains according to power policy control bias.
  43. Sistla, Krishnakanth; Mulla, Dean; Garg, Vivek; Rowland, Mark; Doraiswamy, Suresh; Srinivasa, Ganapati; Gilbert, Jeffrey D., Dynamically adjusting power of non-core processor circuitry including buffer circuitry.
  44. Sistla, Krishnakanth; Mulla, Dean; Garg, Vivek; Rowland, Mark; Doraiswamy, Suresh; Srinivasa, Ganapati; Gilbert, Jeffrey D., Dynamically adjusting power of non-core processor circuitry including buffer circuitry.
  45. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Weissmann, Eliezer; Shulman, Nadav, Dynamically allocating a power budget over multiple domains of a processor.
  46. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Weissmann, Eliezer; Shulman, Nadav, Dynamically allocating a power budget over multiple domains of a processor.
  47. Ananthakrishnan, Avinash N.; Rotem, Efraim; Rajwan, Doron; Weissmann, Eliezer; Shulman, Nadav, Dynamically allocating a power budget over multiple domains of a processor.
  48. Bhandaru, Malini K.; Dehaemer, Eric J.; Shrall, Jeremy J., Dynamically computing an electrical design point (EDP) for a multicore processor.
  49. Ananthakrishnan, Avinash N.; Rotem, Efraim; Weissmann, Eliezer; Rajwan, Doron; Shulman, Nadav; Naveh, Alon; Abu-Salah, Hisham, Dynamically controlling cache size to maximize energy efficiency.
  50. Ananthakrishnan, Avinash N.; Rotem, Efraim; Weissmann, Eliezer; Rajwan, Doron; Shulman, Nadav; Naveh, Alon; Abu-Salah, Hisham, Dynamically controlling cache size to maximize energy efficiency.
  51. Ananthakrishnan, Avinash N.; Rotem, Efraim; Weissmann, Eliezer; Rajwan, Doron; Shulman, Nadav; Naveh, Alon; Abu-Salah, Hisham, Dynamically controlling cache size to maximize energy efficiency.
  52. Bhandaru, Malini K.; Varma, Ankush; Vash, James R.; Wong-Chan, Monica; Dehaemer, Eric J.; Poirier, Sr., Christopher Allan; Bobholz, Scott P., Dynamically controlling interconnect frequency in a processor.
  53. Kupermann, Eli; Agranovsky, Elena, Dynamically controlling power management of an on-die memory of a processor.
  54. Varma, Ankush; Sistla, Krishnakanth V.; Rowland, Martin T.; Garg, Vivek; Burns, James S., Dynamically measuring power consumption in a processor.
  55. Sistla, Krishnakanth V.; Rowland, Mark; Varma, Ankush; Steiner, Ian M.; Bace, Matthew; Borkowski, Daniel; Garg, Vivek; Akturan, Chelsea; Ananthakrishnan, Avinash N., Dynamically modifying a power/performance tradeoff based on a processor utilization.
  56. Sistla, Krishnakanth V.; Rowland, Mark; Varma, Ankush; Steiner, Ian M.; Bace, Matthew; Borkowski, Daniel; Garg, Vivek; Akturan, Cagdas; Ananthakrishnan, Avinash N., Dynamically modifying a power/performance tradeoff based on processor utilization.
  57. Lee, Victor W.; Bai, Yuxin, Dynamically updating a power management policy of a processor.
  58. Zobel, Shmuel; Levit, Maxim; Rotem, Efraim; Weissmann, Eliezer; Rajwan, Doron; Shapira, Dorit; Shulman, Nadav, Dynamically updating at least one power management operational parameter pertaining to a turbo mode of a processor for increased performance.
  59. Varma, Ankush; Sistla, Krishnakanth V.; Sotomayor, Guy G.; Henroid, Andrew D.; Gough, Robert E.; Schiff, Tod F., Dynamically updating logical identifiers of cores of a processor.
  60. Sugumar, Suresh; Kumashikar, Mahesh K.; Pal, Rahul; Muthrasanallur, Sridhar, Early wake-warn for clock gating control.
  61. Morisawa, Toshikazu, Electronic apparatus and method of setting an operation mode of the same.
  62. Ananthakrishnan, Avinash N.; Sodhi, Inder M.; Rotem, Efraim; Rajwan, Doron; Weissmann, Eliezer; Wells, Ryan, Enabling a non-core domain to control memory bandwidth in a processor.
  63. Ananthakrishnan, Avinash N.; Sodhi, Inder M.; Rotem, Efraim; Rajwan, Doron; Weissmann, Eliezer; Wells, Ryan, Enabling a non-core domain to control memory bandwidth in a processor.
  64. Ananthakrishnan, Avinash N.; Sodhi, Inder M.; Rotem, Efraim; Rajwan, Doron; Weissmann, Eliezer; Wells, Ryan, Enabling a non-core domain to control memory bandwidth in a processor.
  65. Ananthakrishnan, Avinash N.; Sodhi, Inder M.; Rotem, Efraim; Rajwan, Doron; Wiessman, Eliezer; Wells, Ryan, Enabling a non-core domain to control memory bandwidth in a processor.
  66. Ananthakrishnan, Avinash N.; Gunther, Stephen H.; Shrall, Jeremy J.; Schwartz, Jay D., Estimating scalability value for a specific domain of a multicore processor based on active state residency of the domain, stall duration of the domain, memory bandwidth of the domain, and a plurality of coefficients based on a workload to execute on the domain.
  67. Ananthakrishnan, Avinash N.; Rotem, Efraim; Feit, Itai; Ziv, Tomer; Rajwan, Doron; Shulman, Nadav; Naveh, Alon, Estimating temperature of a processor core in a low power state without thermal sensor information.
  68. Weissmann, Eliezer; Aizik, Yoni; Rajwan, Doron; Rosenzweig, Nir; Rotem, Efraim; Cooper, Barnes; Diefenbaugh, Paul S.; Therien, Guy M.; Mishaeli, Michael; Shulman, Nadav; Melamed, Ido; Tokman, Niv; Gendler, Alexander; Gihon, Arik; Sabin, Yevgeni; Salah, Hisham Abu; Natanzon, Esfir, Forcing a processor into a low power state.
  69. Varma, Ankush; Sistla, Krishnakanth V.; Chu, Allen W.; Steiner, Ian M., Forcing core low power states in a processor.
  70. Burns, James S.; Ganesan, Baskaran; Fenger, Russell J.; Bodas, Devadatta V.; Iyengar, Sundaravarathan R.; Nelson, Feranak; Powell, Jr., John M.; Sugumar, Suresh, Increasing power efficiency of turbo mode operation in a processor.
  71. Burns, James S.; Ganesan, Baskaran; Fenger, Russell J.; Bodas, Devadatta V.; Iyengar, Sundaravarathan R.; Nelson, Feranak; Powell, Jr., John M.; Sugumar, Suresh, Increasing power efficiency of turbo mode operation in a processor.
  72. Burns, James S.; Ganesan, Baskaran; Fenger, Russell J.; Bodas, Devadatta V.; Iyengar, Sundaravarathan R.; Nelson, Feranak; Powell, Jr., John M.; Sugumar, Suresh, Increasing power efficiency of turbo mode operation in a processor.
  73. Guddeti, Jayakrishna; Bhattacharyya, Binata, Increasing turbo mode residency of a processor.
  74. Guddeti, Jayakrishna; Bhattacharyya, Binata, Increasing turbo mode residency of a processor.
  75. Guddeti, Jayakrishna; Bhattacharyya, Binata, Increasing turbo mode residency of a processor.
  76. Conrad, Shuan M.; Gunther, Stephen H.; Shrall, Jeremy J.; Deval, Anant S.; Jahagirdar, Sanjeev S., Independent control of processor core retention states.
  77. Sodhi, Inder; Jahagirdar, Sanjeev; Wells, Ryan; Offen, Zeev; Sharma, Shalini; Drottar, Ken, Independently controlling frequency of plurality of power domains in a processor system.
  78. Ganor, Assaf; Rotem, Efraim; Winer, Noam; Vikinski, Omer, Integrating a power arbiter in a processor.
  79. Lee, Sejoong; Choi, Soon-Hyeok; Lu, Xiaolin, Limiting the number of unexpected wakeups in a computer system implementing a power-saving preemptive wakeup method from historical data.
  80. Svilan, Vjekoslav; Mackintosh, David N., Managing dynamic capacitance using code scheduling.
  81. Fetzer, Eric; Reidlinger, Reid J.; Soltis, Don; Bowhill, William J.; Shrimali, Satish; Sistla, Krishnakanth; Rotem, Efraim; Kumar, Rakesh; Garg, Vivek; Naveh, Alon; Sharma, Lokesh, Managing power consumption in a multi-core processor.
  82. Fetzer, Eric; Riedlinger, Reid; Soltis, Don; Bowhill, William; Shrimali, Satish; Sistla, Krishnakanth; Rotem, Efraim; Kumar, Rakesh; Garg, Vivek; Naveh, Alon; Sharma, Lokesh, Managing power consumption in a multi-core processor.
  83. Weissmann, Eliezer; Rotem, Efraim; Diefenbaugh, Paul; Therien, Guy; Rosenzweig, Nir, Mapping a performance request to an operating frequency in a processor.
  84. Weissmann, Eliezer; Rotem, Efraim; Diefenbaugh, Paul; Therien, Guy; Rosenzweig, Nir, Mapping a performance request to an operating frequency in a processor.
  85. Gendler, Alexander; Novakovsky, Larisa; Sistla, Krishnakanth V.; Garg, Vivek; Mulla, Dean; Choubal, Ashish V.; Hallnor, Erik G.; Weier, Kimberly C., Masking a power state of a core of a processor.
  86. Conrad, Shaun M.; Shrall, Jeremy J., Method and apparatus for atomic frequency and voltage changes.
  87. Suryanarayanan, Anupama; Merten, Matthew C.; Carlson, Ryan L., Method and apparatus to prevent voltage droop in a computer.
  88. Gendler, Alexander, Method and apparatus to provide telemetry data to a power controller of a processor.
  89. Chandra,Arty; Zeira,Eldad, Method and system for reducing battery consumption in wireless transmit/receive units (WTRUs) employed in a wireless local area network/wireless wide area network (WLAN/WWAN).
  90. Armstrong,Troy David; Eide,Curtis Shannon; Haumont,Jeffery David, Method for detecting and powering off unused I/O slots in a computer system.
  91. Jahagirdar, Sanjeev; George, Varghese; Allarey, Jose; Heit, Eric, Method, apparatus and system to dynamically choose an optimum power state.
  92. Jahagirdar, Sanjeev; George, Varghese; Allarey, Jose; Heit, Eric, Method, apparatus and system to dynamically choose an optimum power state.
  93. Kim, Seongwoo; Shrall, Jeremy; Schwartz, Jay D.; Gunther, Stephen H.; Furrer, Travis C., Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme.
  94. Shah, Ketan R.; Distefano, Eric; Gunther, Stephen H.; Shrall, Jeremy J., Method, apparatus, and system for energy efficiency and energy conservation including configurable maximum processor current.
  95. Jahagirdar, Sanjeev S.; Wells, Ryan; Sodhi, Inder, Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state.
  96. Jahagirdhar, Sanjeev S.; Wells, Ryan; Sodhi, Inder, Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state.
  97. Naveh, Alon; Weissmann, Eliezer; Nathan, Ofer; Shulman, Nadav, Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates.
  98. Naveh, Alon; Weissmann, Eliezer; Nathan, Ofer; Shulman, Nadav, Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates.
  99. Naveh, Alon; Yosef, Yuval; Weissmann, Eliezer; Aggarwal, Anil; Rotem, Efraim; Mendelson, Avi; Ronen, Ronny; Ginzburg, Boris; Mishaeli, Michael; Hahn, Scott D.; Koufaty, David A.; Srinivasa, Ganapati; Therien, Guy, Migrating tasks between asymmetric computing elements of a multi-core processor.
  100. Kim, Daehyun; Park, Jong Soo; Woo, Dong Hyuk; Yoo, Richard M.; Hughes, Christopher J., Monitoring vector lane duty cycle for dynamic optimization.
  101. Conroy, David G.; Sotomayor, Guy, Multi-core power management.
  102. Lodolo,Luca; Yi,Hyejung, Multiple functionality associated with a computer ON/OFF pushbutton switch.
  103. Man, Xiuting C.; Derr, Michael N.; Schwartz, Jay D.; Gunther, Stephen H.; Shrall, Jeremy J.; Conrad, Shaun M.; Ananthakrishan, Avinash N., Performing cross-domain thermal control in a processor.
  104. Man, Xiuting C.; Derr, Michael N.; Schwartz, Jay D.; Gunther, Stephen H.; Shrall, Jeremy J.; Conrad, Shaun M.; Ananthakrishnan, Avinash N., Performing cross-domain thermal control in a processor.
  105. Varma, Ankush; Sistla, Krishnakanth V.; Srinivasan, Vasudevan; Gorbatov, Eugene; Henroid, Andrew D.; Cooper, Barnes; Browning, David W.; Therien, Guy M.; Songer, Neil W.; Hermerding, II, James G., Performing dynamic power control of platform devices.
  106. Varma, Ankush; Sistla, Krishnakanth V.; Steiner, Ian M.; Garg, Vivek; Poirier, Chris; Rowland, Martin T., Performing frequency coordination in a multiprocessor system.
  107. Varma, Ankush; Sistla, Krishnakanth V., Performing frequency coordination in a multiprocessor system based on response timing optimization.
  108. Lee, Victor W.; Grochowski, Edward T.; Kim, Daehyun; Bai, Yuxin; Li, Sheng; Mellempudi, Naveen K.; Kalamkar, Dhiraj D., Performing power management in a multicore processor.
  109. Lee, Victor W.; Kim, Daehyun; Bai, Yuxin; Ji, Shihao; Li, Sheng; Kalamkar, Dhiraj D.; Mellempudi, Naveen K., Performing power management in a multicore processor.
  110. Wang, Ren; Samih, Ahmad; Delano, Eric; Shah, Pinkesh J.; Chishti, Zeshan A.; Maciocco, Christian; Tai, Tsung-Yuan Charlie, Power gating a portion of a cache memory.
  111. Wang, Ren; Samih, Ahmad; Delano, Eric; Shah, Pinkesh J.; Chishti, Zeshan A.; Maciocco, Christian; Tai, Tsung-Yuan Charlie, Power gating a portion of a cache memory.
  112. Klaffenbach, David K.; Campin, Michael J.; Gudaitis, Algird M.; Stryker, Chadwick W.; Boehm, Jon S., Power supply circuit.
  113. Kato,Kazuomi; Yamamoto,Tetsuji, Power-saving processing unit, power-saving processing method and program record medium.
  114. Song, Justin J.; Diao, Qian, Predicting future power level states for processor cores.
  115. Song, Justin; Diao, Qian, Predicting future power level states for processor cores.
  116. Song, Justin; Diao, Qian, Predicting future power level states for processor cores.
  117. Aizik, Yoni; Weissmann, Eliezer; Rotem, Efraim; Sabin, Yevgeni; Rajwan, Doron; Yasin, Ahmad, Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency.
  118. Diamand, Israel; Rubinstein, Asaf; Gihon, Arik; Kuzi, Tal; Ziv, Tomer; Shulman, Nadav, Programmable power management agent.
  119. Conrad, Neena; Conrad, Shaun M.; Gunther, Stephen H., Providing an inter-arrival access timer in a processor.
  120. Bhandaru, Malini K.; Dehaemer, Eric J., Providing energy efficient turbo operation of a processor.
  121. Kumar, Pankaj; Nguyen, Hang T.; Houghton, Christopher; Biermann, David A., Providing per core voltage and frequency control.
  122. Kumar, Pankaj; Nguyen, Hang T.; Houghton, Christopher; Biermann, David A., Providing per core voltage and frequency control.
  123. Kumar, Pankaj; Nguyen, Hang T.; Houghton, Christopher; Biermann, David A., Providing per core voltage and frequency control.
  124. Kumar, Pankaj; Nguyen, Hang T.; Houghton, Christopher; Biermann, David A., Providing per core voltage and frequency control.
  125. Kumar, Pankaj; Nguyen, Hang T.; Houghton, Christopher; Biermann, David A., Providing per core voltage and frequency control.
  126. Kumar, Pankaj; Nguyen, Hang T.; Houghton, Christopher; Biermann, David A., Providing per core voltage and frequency control.
  127. Kumar, Pankaj; Nguyen, Hang; Houghton, Christopher; Biermann, David A., Providing per core voltage and frequency control.
  128. Sodhi, Inder M.; Cooper, Barnes; Diefenbaugh, Paul S.; Siddiqi, Faraz A.; Calyer, Michael; Henroid, Andrew D.; Singh, Ruchika, Rescheduling workloads to enforce and maintain a duty cycle.
  129. Gendler, Alexander; Leifman, George, Restricting clock signal delivery based on activity in a processor.
  130. Gendler, Alexander; Rotem, Efraim; Mandelblat, Julius; Lyakhov, Alexander; Novakovsky, Larisa; Leifman, George; Makovsky, Lev; Sabba, Ariel; Tokman, Niv, Restricting clock signal delivery in a processor.
  131. Ramani, Sundar; Raman, Arvind; Mandhani, Arvind; Choubal, Ashish V.; Muthukumar, Kalyan; Durg, Ajaya V.; Chakki, Samudyatha, Selecting a low power state based on cache flush latency determination.
  132. Ramani, Sundar; Raman, Arvind; Mandhani, Arvind; Choubal, Ashish V.; Muthukumar, Kalyan; Durg, Ajaya V.; Chakki, Samudyatha, Selecting a low power state based on cache flush latency determination.
  133. Shikata,Takashi; Satoh,Taizoh; Hiji,Yoshihiro; Hirata,Takuya, Semiconductor device with a hardware mechanism for proper clock control.
  134. Mann, Xiuting C.; Ananthakrishnan, Avinash; Derr, Michael N.; Forbell, Craig, Sharing power between domains in a processor package using encoded power consumption information from a second domain to calculate an available power budget for a first domain.
  135. Klaffenbach,David K.; Campin,Michael J.; Gudaitis,Algird M.; Stryker,Chadwick W., System and method for determining the power drawn from a switching power supply by counting the number of times a switching power supply switch is enabled.
  136. Suryanarayanan, Anupama; Ananthakrishnan, Avinash N.; Ashok, Chinmay; Shrall, Jeremy J., Techniques to enable communication between a processor and voltage regulator.
  137. Sistla, Krishnakanth V.; Shrall, Jeremy; Gunther, Stephen H.; Rotem, Efraim; Naveh, Alon; Weissmann, Eliezer; Aggarwal, Anil; Rowland, Martin T.; Varma, Ankush; Steiner, Ian M.; Bace, Matthew; Ananthakrishnan, Avinash N.; Brandt, Jason, User level control of power management policies.
  138. Sistla, Krishnakanth V.; Shrall, Jeremy; Gunther, Stephen H.; Rotem, Efraim; Naveh, Alon; Weissmann, Eliezer; Aggarwal, Anil; Rowland, Martin T.; Varma, Ankush; Steiner, Ian M.; Bace, Matthew; Ananthakrishnan, Avinash N.; Brandt, Jason, User level control of power management policies.
  139. Sistla, Krishnakanth V.; Shrall, Jeremy; Gunther, Stephen H.; Rotem, Efraim; Naveh, Alon; Weissmann, Eliezer; Aggarwal, Anil; Rowland, Martin T.; Varma, Ankush; Steiner, Ian M.; Bace, Matthew; Ananthakrishnan, Avinash N.; Brandt, Jason, User level control of power management policies.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로