초록 ▼

A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves e

A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

대표청구항 ▼

1. A method of making a parallel plate capacitor in an integrated circuit employing copper interconnects, comprising the steps of: forming devices and lower level interconnects, at least some of which are formed from copper, of said integrated circuit, including a set of top lower level interconne

1. A method of making a parallel plate capacitor in an integrated circuit employing copper interconnects, comprising the steps of: forming devices and lower level interconnects, at least some of which are formed from copper, of said integrated circuit, including a set of top lower level interconnects; forming an initial capacitor stack comprising a first cap layer having a first cap thickness, a conductive bottom plate layer disposed over said first cap layer, a capacitor dielectric layer disposed over said conductive bottom plate layer, a conductive top plate layer disposed over said capacitor dielectric layer, and a second cap layer having a second cap thickness disposed over said conductive top plate layer; etching said second cap layer and said top plate layer, stopping on said capacitor dielectric layer, to form a capacitor top plate covered by said second cap layer, said capacitor top plate being contained within a capacitor area that is offset from a closest one of said set of top lower level interconnects by at least a minimum offset distance; forming a third cap layer having a third cap thickness, whereby exposed portions of said capacitor dielectric layer are covered by said third cap layer and said conductive top plate is covered by a top plate cap layer having a top plate cap thickness substantially equal to the sum of said second and third cap thicknesses; etching said third cap layer, said capacitor dielectric layer and said bottom plate layer, thereby forming a capacitor bottom plate covering said capacitor area and extending past said capacitor top plate on all sides, whereby all edges of said capacitor bottom plate are offset laterally from corresponding edges of said capacitor top plate by at least a top plate offset distance; depositing a layer of interlayer dielectric; forming a set of via apertures in said interlayer dielectric, stopping on said first and third cap layers; removing all of said third cap layer in a bottom plate contact area above said bottom plate and outside said top plate and removing only a portion of said third cap layer above said top plate in a top plate contact area, leaving a remaining thickness of said third cap layer in said top plate contact area; removing said capacitor dielectric in said bottom plate contact area; removing all of said remaining thickness of said third cap layer in said top plate contact area; and forming capacitor interconnect members of a set of upper level interconnects in said top plate contact area and said bottom plate contact area. 2. A method according to claim 1, in which said bottom plate layer is a composite layer comprising a lower highly conductive layer and an upper conductive barrier layer and said step of removing said capacitor dielectric in said bottom plate contact area penetrates only said upper conductive barrier layer.3. A method according to claim 1, in which a liner material is deposited in said top plate contact area and said bottom plate contact area; and a layer of copper is deposited above said liner material and patterned to form said set of upper level interconnects. 4. A method according to claim 1, in which: said step of forming a set of via apertures in said interlayer dielectric includes simultaneously forming via apertures for said set of upper level interconnects; said step of removing only a portion of said third cap layer above said top plate includes simultaneously removing only a portion of said third cap layer in said via apertures for said set of upper level interconnects; said step of removing all of said remaining thickness of said third cap layer in said top plate contact area includes simultaneously removing all of said remaining thickness of said third cap layer in said via apertures for said set of upper level interconnects; and said step of forming capacitor interconnect members of a set of upper level interconnects in said top plate contact area and said bottom plate c ontact area includes simultaneously forming capacitor interconnect members for said set of upper level interconnects. 5. A method according to claim 1, in which said capacitor interconnect members are aluminum.