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Field programmable gate array and microcontroller system-on-a-chip 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/80
  • G06F-013/42
출원번호 US-0654237 (2000-09-02)
발명자 / 주소
  • Kundu, Arunangshu
  • Goldfein, Arnold
  • Plants, William C.
  • Hightower, David
출원인 / 주소
  • Actel Corporation
대리인 / 주소
    Sierra Patent Group, Ltd.
인용정보 피인용 횟수 : 63  인용 특허 : 5

초록

An system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the

대표청구항

1. An integrated circuit comprising: a field programmable gate array (FPGA) core having logic clusters and static random access memory modules; a FPGA virtual component interface translator coupled to the FPGA core and configured to translate signals from a first protocol to a second protocol;

이 특허에 인용된 특허 (5)

  1. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
  2. Meyer Thomas John ; Anderson Bruce James ; Liu Tianmin, Method and apparatus for providing control channel communications for an information distribution system.
  3. van der Wal Gooitzen Siemen ; Hansen Michael Wade ; Piacentino Michael Raymond ; Brehm Frederic William, Modular parallel-pipelined vision system for real-time video processing.
  4. Klsters Paul (Pfaffenhofen a.d. Ilm DEX), Process for the production of isohumulones.
  5. Elgamal Abbas (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Mohsen Amr (Saratoga CA), User programmable integrated circuit interconnect architecture and test method.

이 특허를 인용한 특허 (63)

  1. Kadota,Daisuke, Access control device for bus bridge circuit and method for controlling the same.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  8. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  9. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  10. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  15. Hogenauer, Eugene B., Arithmetic node including general digital signal processing functions for an adaptive computing machine.
  16. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  17. Zievers, Peter J., Computing system with hardware bus management and method of operation thereof.
  18. Zievers, Peter J., Computing system with hardware bus management and method of operation thereof.
  19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  20. Späh, Jürgen, Configurable interface circuit.
  21. Ryser,Peter, Configuration logic for embedded software.
  22. Plants,William C.; Kundu,Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
  23. Plants,William C.; Kundu,Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
  24. Plants,William C.; Kundu,Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
  25. Khan, Shoab Ahmad; Rahmatullah, Muhammad Mohsin, Distributed processing architecture with scalable processing layers.
  26. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  27. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  28. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  29. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  30. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  31. Kundu, Arunangshu; Goldfein, Arnold; Plants, William C.; Hightower, David, Field programmable gate array and microcontroller system-on-a-chip.
  32. Kundu, Arunangshu; Goldfein, Arnold; Plants, William C.; Hightower, David, Field programmable gate array and microcontroller system-on-a-chip.
  33. Kundu,Arunangshu; Goldfein,Arnold; Plants,William C.; Hightower,David, Field programmable gate array and microcontroller system-on-a-chip.
  34. Conover,Kurt M.; Linn,John H.; Schreiber,Anita L., First-in-first-out memory system and method for providing same.
  35. Feng,Sheng; Liu,Tong; Lien,Jung Cheun, Inter-tile buffer system for a field programmable gate array.
  36. Cooke, Laurence H.; Lu, Alexander, Interface configurable for use with target/initiator signals.
  37. Cooke,Laurence H.; Lu,Alexander, Interface configurable for use with target/initiator signals.
  38. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  39. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  40. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  41. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  42. Mohan, Sundararajarao; Ganesan, Satish R.; Bilski, Goran, Method and system for function acceleration using custom instructions.
  43. Hwang,L. James; Sanchez,Reno L., Method and system for integrating cores in FPGA-based system-on-chip (SoC).
  44. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  45. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  46. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  47. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  48. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  49. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  50. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  51. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  52. Pang, Jon Laurent; Usman, Mohammad; Khan, Shoab Ahmad; Rahmatullah, Muhammad Mohsin, Methods and systems for managing variable delays in packet transmission.
  53. Kundu,Arunangshu; Narayanan,Venkatesh; McCollum,John; Plants,William C., Multi-level routing architecture in a field programmable gate array having transmitters and receivers.
  54. Sun, Shin Nan; Wong, Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
  55. Agarwal, Anant, Processing data in a parallel processing environment.
  56. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  57. Wang, Seongmoon; Chakradhar, Srimat T.; Balakrishnan, Kedarnath J., Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards.
  58. Ramesh, Tirumale K., Scalable FPGA fabric architecture with protocol converting bus interface and reconfigurable communication path to SIMD processing elements.
  59. Zack,Steven J.; Allaire,William E., Split FIFO configuration of block RAM.
  60. Master,Paul L.; Watson,John, Storage and delivery of device features.
  61. Gentieu,Paul R.; Acquistapace,Tom; Iryami,Farhad, Synchronous network traffic processor.
  62. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  63. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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