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Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/00
출원번호 US-0633831 (2000-08-07)
발명자 / 주소
  • Juan, Yujen
출원인 / 주소
  • Transwitch Corporation
대리인 / 주소
    Gordon & Jacobson, P.C.
인용정보 피인용 횟수 : 63  인용 특허 : 21

초록

An improved mechanism for performing different types of digital signal processing functions, including correlation, sorting, and filtering operations. The mechanism includes a plurality of computational cells which can be dynamically configured (and reconfigured) in parallel to perform the different

대표청구항

1. A method for performing a digital signal processing operation comprising:providing a configurable computation engine including a plurality of M computation cells, where M is an integer greater than two, each given computation cell including at least one storage element, a comparator that compares

이 특허에 인용된 특허 (21)

  1. Dawes Robert L. (Allen TX), Adaptive processing system having an array of individually configurable processing components.
  2. Lloyd Scott Edward (Mesa AZ) Pan Shao Wei (Schaumburg IL) Wang Shay-Ping Thomas (Long Grove IL), Computer processor having a pipelined architecture which utilizes feedback and method of using same.
  3. Elings Virgil B. (P.O. Box 6463 Santa Barbara CA 93111) Nicoli David F. (448 Mills Way Goleta CA 93017), Correlator.
  4. Sakiyama Shiro (Kadoma JPX) Maruyama Masakatsu (Hirakata JPX), Digital filter and digital signal processing system.
  5. Maulik Prabir C. ; Mandeep Chadha S. ; Kan Zhao, Efficient and scalable FIR filter architecture for decimation.
  6. Retter Rafi,ILX ; Manor Yonatan,ILX ; Bar David,ILX ; Mahlab Shlomo,ILX ; Aboutboul Ronny,ILX, Enhanced DSP apparatus.
  7. Tiemann Jerome Johnson ; Harrison Daniel David, Low power parallel correlator for measuring correlation between digital signal segments.
  8. Kodra Gregg S. (Austin TX), Method and apparatus for a finite impulse response filter processor.
  9. Kolchinsky Alexander (Andover MA), Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of da.
  10. Gorshtein Valery Y.,RUX ; Efremova Olga A.,RUX, Multifunctional execution unit having independently operable adder and multiplier.
  11. Ueda Hirotada (Kokubunji JPX) Kato Kanji (Tokorozawa JPX) Matsushima Hitoshi (Tachikawa JPX), Multiprocessor system.
  12. Kato Hideki (Kawasaki JPX) Yoshizawa Hideki (Kawasaki JPX) Iciki Hiroki (Kawasaki JPX) Masumoto Daiki (Kawasaki JPX), Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connec.
  13. Ogletree Thomas M., Parallel multiply accumulate array circuit.
  14. Chang Chi-Yung (Torrance CA) Fang Wai-Chi (San Marino CA) Curlander John C. (Pasadena CA), Pipeline synthetic aperture radar data compression utilizing systolic binary tree-searched architecture for vector quant.
  15. Cavallotti Franco (Turin ITX) Cremonesi Alessandro (Angelo Lodigiano ITX) Poluzzi Rinaldo (Milan ITX), Programmable digital filter.
  16. Dujardin Eric,FRX ; Gay-Bellile Olivier,FRX, Programmable processor circuit with a reconfigurable memory for realizing a digital filter.
  17. Hsu William ; Yin Taiwei, Reduction of execution times for convolution operations.
  18. Dao Tuan Q. ; Steiss Donald E., Shared floating-point unit in a single chip multiprocessor.
  19. Lorenz Dietmar,DEX ; Bauer Harald,DEX ; Dietsch Rainer,DEX ; Hellwig Karl,DEX, Signal processor.
  20. Lee Chen-Yi (Hsinchu TWX) Tsai Jer-Min (Hsinchu TWX) Hsieh Po-Wen (Hsinchu TWX), Sorter structure based on shiftable content memory.
  21. Wheeler James E. (Schenectady NY) Hardy Robert M. (Scotia NY) Dunki-Jacobs Robert J. (Saratoga NY) Premerlani William J. (Scotia NY), VLSI programmable digital signal processor.

이 특허를 인용한 특허 (63)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  2. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
  3. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
  4. Oates,John H., Computational methods for use in a short-code spread-spectrum communications system.
  5. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  6. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  7. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  8. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  9. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  10. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  11. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
  12. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
  13. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
  14. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  15. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  16. Oates,John H., Load balancing computational methods in a short-code spread-spectrum communications system.
  17. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  18. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  19. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  20. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  21. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  22. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  23. Vorbach, Martin, Method for debugging reconfigurable architectures.
  24. Vorbach, Martin, Method for debugging reconfigurable architectures.
  25. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  26. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  27. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
  28. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  29. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  30. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  31. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  32. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  35. Vorbach, Martin, Methods and devices for treating and/or processing data.
  36. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
  37. Hou,Yan; Jiang,Hong; Leung,Kam, Performance optimized approach for efficient numerical computations.
  38. Hou,Yan; Jiang,Hong; Leung,Kam, Performance optimized approach for efficient numerical computations.
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  41. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  42. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  43. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  44. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  45. Ozawa,Kunihiko, Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system.
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  48. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
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  53. Vorbach, Martin; Bretz, Daniel, Router.
  54. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
  55. Oates,John H.; Imperiali,Steven R.; Fuchs,Alden J.; Jacques,Kathleen J.; Greene,Jonathan E.; Jenkins,William J.; Lauginiger,Frank P.; Majchrzak,David E.; Cantrell,Paul E.; Cifric,Mirza; Dunn,Ian N.; Vinskus,Michael J., Wireless communication systems and methods for contiguously addressable memory enabled multiple processor based multiple user detection.
  56. Oates,John H., Wireless communication systems and methods for long-code communications for regenerative multiple user detection involving implicit waveform subtraction.
  57. Oates,John H., Wireless communication systems and methods for long-code communications for regenerative multiple user detection involving pre-maximal combination matched filter outputs.
  58. Oates,John H.; Imperiali,Steven R.; Fuchs,Alden J.; Jacques,Kathleen J.; Greene,Jonathan E.; Jenkins,William J.; Lauginiger,Frank P.; Majchrzak,David E.; Cantrell,Paul E.; Cifric,Mizra; Dunn,Ian N.; Vinskus,Michael J., Wireless communications systems and methods for cache enabled multiple processor based multiple user detection.
  59. Oates,John H.; Imperiali,Steven R.; Fuchs,Alden J.; Jacques,Kathleen J.; Greene,Jonathan E.; Jenkins,William J.; Lauginiger,Frank P.; Majchrzak,David E.; Cantrell,Paul E.; Cifric,Mirza; Dunn,Ian N.; Vinskus,Michael J., Wireless communications systems and methods for multiple operating system multiple user detection.
  60. Oates,John H.; Imperiali,Steven R.; Fuchs,Alden J.; Jacques,Kathleen J.; Greene,Jonathan E.; Jenkins,William J.; Lauginiger,Frank P.; Majchrzak,David E.; Cantrell,Paul E.; Cifric,Mirza; Dunn,Ian N.; , Wireless communications systems and methods for multiple processor based multiple user detection.
  61. Oates,John H.; Imperiali,Steven R.; Fuchs,Alden J.; Jacques,Kathleen J.; Greene,Jonathan E.; Jenkins,William J.; Lauginiger,Frank P.; Majchrzak,David E.; Cantrell,Paul E.; Cifric,Mirza; Dunn,Ian N.; , Wireless communications systems and methods for nonvolatile storage of operating parameters for multiple processor based multiple user detection.
  62. Oates,John H., Wireless communications systems and methods for short-code multiple user detection.
  63. Oates,John H.; Greene,Jonathan E., Wireless communications systems and methods for virtual user based multiple user detection utilizing vector processor generated mapped cross-correlation matrices.
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