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Multilayer structure with controlled internal stresses and making same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/02
  • B32B-005/00
출원번호 US-0913006 (2000-02-09)
우선권정보 FR-1999-901558 (1999-02-10)
국제출원번호 PCT/FR00/00308 (2000-02-09)
국제공개번호 WO00/48238 (2000-08-17)
발명자 / 주소
  • Moriceau, Hubert
  • Rayssac, Olivier
  • Cartier, Anne-Marie
  • Aspar, Bernard
출원인 / 주소
  • Commissariat a l'Energie Atomique
대리인 / 주소
    Anderson Kill + Olick, P.C.
인용정보 피인용 횟수 : 38  인용 특허 : 10

초록

A multilayer structure with controlled internal stresses comprising, in this order, a first main layer ( 110 a ), at least a first constraint adaptation layer ( 130 ) in contact with the first main layer, at least a second stress adaptation layer ( 120 ) put into contact by adhesion with said firs

대표청구항

1. Method for producing a multilayer structure having a defined geometrical orientation from at least a first main layer and a second main layer comprising the steps of:(a) providing the first main layer with a first stress adaptation layer and providing at least a second stress adaptation layer bet

이 특허에 인용된 특허 (10)

  1. Linn Jack H. (Melbourne FL) Lowry Robert K. (Melbourne Beach FL) Rouse George V. (Indiatlantic FL) Buller James F. (Austin TX) Speece William H. (Palm Bay FL), Bonded wafer processing.
  2. Biebl Markus,DEX, Method for producing a layer with reduced mechanical stresses.
  3. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Method for producing semiconductor substrate.
  4. Mori Kazuo,JPX, Method of bonding a III-V group compound semiconductor layer on a silicon substrate.
  5. Tejwani Manu J. (Yorktown Heights NY) Iyer Subramanian S. (Yorktown Heights NY), Method of forming an ultra-uniform silicon-on-insulator layer.
  6. Pinker Ronald D. (Peekskill NY) Arnold Emil (Chappaqua NY) Baumgart Helmut (Mahopac NY), Process for making strain-compensated bonded silicon-on-insulator material free of dislocations.
  7. Egloff Richard, Process for production of thin layers of semiconductor material.
  8. Ohmi Tadahiro,JPX ; Tanaka Nobuyoshi,JPX ; Ushiki Takeo,JPX ; Shinohara Toshikuni,JPX ; Nitta Takahisa,JPX, SOI bonding structure.
  9. Moslehi Mehrdad M. (Dallas TX), SOI/semiconductor heterostructure fabrication by wafer bonding.
  10. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Semiconductor substrate and method of manufacturing the same.

이 특허를 인용한 특허 (38)

  1. Hirsch, Michele; Guenther, Michael, Composite component and method for producing a composite component.
  2. Aida, Hideo; Aota, Natsuko; Takeda, Hidetoshi; Honjo, Keiji; Hoshino, Hitoshi; Ogasawara, Mai, Composite substrate manufacturing method, semiconductor element manufacturing method, composite substrate, and semiconductor element.
  3. Hammerich, Reiner P.; Chadzelek, Thomas, Computer software adaptation method and system.
  4. Moriceau, Hubert; Roussin, Jean-Claude, Deformation moderation method.
  5. Aspar, Bernard; Moriceau, Hubert; Zussy, Marc; Rayssac, Olivier, Detachable substrate or detachable structure and method for the production thereof.
  6. Gmitter, Thomas; He, Gang; Hegedus, Andreas, Epitaxial lift off stack having a non-uniform handle and methods thereof.
  7. Gmitter, Thomas; He, Gang; Hegedus, Andreas, Epitaxial lift off stack having a non-uniform handle and methods thereof.
  8. Archer, Melissa; Atwater, Harry; Gmitter, Thomas; He, Gang; Hegedus, Andreas; Higashi, Gregg; Sonnenfeldt, Stewart, Epitaxial lift off stack having a pre-curved handle and methods thereof.
  9. Archer, Melissa; Atwater, Harry; Gmitter, Thomas; He, Gang; Hegedus, Andreas; Higashi, Gregg; Sonnenfeldt, Stewart, Epitaxial lift off stack having a pre-curved handle and methods thereof.
  10. Joly, Jean-Pierre; Ulmer, Laurent; Parat, Guy, Integrated circuit on high performance chip.
  11. Kawakami, Akira, Method for fabricating thin layer device.
  12. Fournel, Franck; Moriceau, Hubert; Lagahe, Christelle, Method for making a stressed structure designed to be dissociated.
  13. Deguet, Chrystel; Clavelier, Laurent, Method for making a thin-film element.
  14. Rossini, Umberto; Eleouet, Raphaël; Flahaut, Thierry, Method for manufacturing a multilayer structure on a substrate.
  15. Yeh, Chin-Wen; Peng, Zhi-Jian, Method for manufacturing anti-electromagnetic interference shields.
  16. Takeuchi,Kunio; Kunoh,Yasumitsu, Method for manufacturing nitride-base semiconductor element and nitride-base semiconductor element.
  17. Tauzin, Aurélie; Dechamp, Jérôme; Mazen, Frédéric; Madeira, Florence, Method for preparing thin GaN layers by implantation and recycling of a starting substrate.
  18. Nguyen, Nguyet-Phuong; Cayrefourcq, Ian; Lagahe-Blanchard, Christelle; Bourdelle, Konstantin; Tauzin, Aurélie; Fournel, Franck, Method for self-supported transfer of a fine layer by pulsation after implantation or co-implantation.
  19. Moriceau,Hubert; Fournel,Frank; Aspar,Bernard, Method for separating wafers bonded together to form a stacked structure.
  20. Faure, Bruce; Marcovecchio, Alexandra, Method of fabricating a composite structure with a stable bonding layer of oxide.
  21. Coffin, Jeffrey T.; Gaynes, Michael A.; Questad, David L.; Sikka, Kamal K.; Toy, Hilton T.; Wakil, Jamil A., Method of forming a flip-chip package.
  22. Jin, Sung-Hun, Method of manufacturing amorphous IGZO TFT-based transient semiconductor.
  23. Deguet, Chrystel; Clavelier, Laurent; Dechamp, Jerome, Method of transferring a thin film onto a support.
  24. Fournel, Franck, Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer.
  25. Wasshuber,Christoph; Joyner,Keith A., Methods and apparatus for inducing stress in a semiconductor device.
  26. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming III-V semiconductor device structures.
  27. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain.
  28. Sadaka, Mariam; Aspar, Bernard; Blanchard, Chrystelle Lagahe, Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices.
  29. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods of forming strained-semiconductor-on-insulator device structures.
  30. Ito, Korekiyo, Piezoelectric device and method for manufacturing piezoelectric device.
  31. Moriceau, Hubert; Bruel, Michel; Aspar, Bernard; Maleville, Christophe, Process for the transfer of a thin film.
  32. Moriceau, Hubert; Bruel, Michel; Aspar, Bernard; Maleville, Christophe, Process for the transfer of a thin film comprising an inclusion creation step.
  33. Hara,Kazumi, Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same.
  34. Orlowski,Marius K.; Adams,Vance H., Semiconductor device and method for regional stress control.
  35. Hannebauer, Robert, Semiconductor device and method of manufacturing the same.
  36. Orlowski,Marius K.; Adams,Vance H., Semiconductor device having a plurality of different layers and method therefor.
  37. Sinha, Nishant; Sandhu, Gurtej S.; Smythe, John, Semiconductor material manufacture.
  38. Le Vaillant, Yves-Matthieu, Substrate with determinate thermal expansion coefficient.
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