Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G11C-029/00
출원번호
US-0338928
(2003-01-08)
발명자
/ 주소
LaRosa, Giuseppe
Strong, Alvin W.
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Shkurko Eugene
인용정보
피인용 횟수 :
45인용 특허 :
1
초록▼
An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout me
An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout mechanisms that become activate during the charge transfer as well as during storage under operating or burn-in conditions. The on-chip circuit forces and senses a voltage to an individual DRAM storage capacitor allowing the pulse test methodology characterize the individual storage capacitor charge leakage rate and quantify the rate of charge transfer between the bitline and the storage capacitor in the DRAM cell.
대표청구항▼
1. An apparatus for measuring the transfer characteristics of a charge transfer device and the charge holding capability of a capacitor wherein said charge transfer device and said capacitor are integral to a memory cell, the apparatus comprising:a memory array consisting of a plurality of said memo
1. An apparatus for measuring the transfer characteristics of a charge transfer device and the charge holding capability of a capacitor wherein said charge transfer device and said capacitor are integral to a memory cell, the apparatus comprising:a memory array consisting of a plurality of said memory cells arranged in a matrix formation, wherein at least one of said memory cells is coupled to a bitline and to a wordline;a circuit having two inputs, wherein by applying a constant voltage to the first input of said circuit and by applying a voltage pulse to the second input of said circuit, electrical charge is transferred via a corresponding bitline coupled to the capacitor of said at least one memory cell when a corresponding wordline coupled to said at least one memory cell is activated; anda voltage amplifier for amplifying the voltage in said capacitor and for enabling a transfer of said amplified voltage to a means for performing an analog measurement. 2. The apparatus of claim 1, wherein said circuit includes a common input/output line (I/O) coupled to said at least one memory cell, wherein when said common I/O acts as an input, said means for performing an analog measurement is disconnected, enabling a charge transfer from said bitline to said capacitor, and when said I/O acts as an output, said corresponding bitline is disconnected, enabling said analog measurement. 3. The apparatus of claim 1, wherein said circuit is comprised of first and second passgate transistors coupled to a common I/O line. 4. The apparatus of claim 3, wherein said circuit further comprises an inverter to enable a complementary operation of said first and second passgates. 5. The apparatus recited in claim 4, wherein said circuit comprises a third passgate to inhibit a signal applied to said second input from being measured by said measuring means. 6. The apparatus of claim 1, wherein said amplifier is positioned on-chip. 7. The apparatus of claim 1 wherein the circuit comprises a bit line logic node and a logic circuit, wherein the logic circuit includes a pair of passgates both coupled to the bit line logic node for alternatively blocking the test voltage signals to the one memory cell of the memory cell array while permitting transmitting from the one memory cell the scaled memory cell voltage level and permitting the test voltage signals to the one memory cell of the memory cell array while blocking the transmitting from the one memory cell the scaled memory cell voltage level. 8. The apparatus of claim 7 wherein the logic circuit further includes a first input node and a second input node, the first input node for receiving a selection signal that selects either of said alternatively blocking the test voltage signals while permitting transmitting from the one memory cell or permitting the test voltage signals while blocking the transmitting from the one memory cell, the second input node for receiving one of said test voltage signals for transmitting to the one memory cell of the memory cell array. 9. A method for determining a charge retention performance of a memory cell, the method comprising the steps of:electrically coupling a constant voltage source having a voltage level to the memory cell;electrically connecting a first blocking device (PG 3 ) and a second blocking device (WL transistor) between the constant voltage source and the memory cell;opening the first blocking device and the second blocking device including allowing charge transfer from the constant voltage source to charge the memory cell;closing the first and second blocking devices including preventing the charge transfer to the memory cell and determining a time duration during which the second blocking device is closed;opening the second blocking device while keeping closed the first blocking device including measuring a scaled voltage level of the memory cell; andcalculating a charge retention performance level of the memory cell based on the voltage level of the vol tage source, the measured scaled voltage level of the memory cell, and the time duration. 10. The method of claim 9, wherein the calculating step includes the step of calculating a charge retention time. 11. A method for measuring the transfer characteristics of a charge transfer device and the charge holding capability of a capacitor wherein the charge transfer device and the capacitor are integral to a memory cell, the method steps comprising:providing a memory array consisting of a plurality of said memory cells arranged in a matrix formation, wherein at least one of said memory cells is coupled to a bitline and to a wordline;providing a circuit having two inputs, wherein by applying a constant voltage to the first input of said circuit and by applying a voltage pulse to the second input of said circuit, electrical charge is transferred via a corresponding bitline coupled to the capacitor of said at least one memory cell when the corresponding wordline coupled to said at least on memory cell is activated; andproviding an on-chip voltage amplifier for amplifying the voltage in said capacitor and for enabling the transfer of said amplified voltage to a means for performing an analog measurement. 12. The method of claim 11, wherein said circuit is further comprised of:means for applying a voltage and holding a charge in said capacitor without allowing for a charge transfer to occur;means for transferring the charge stored in said capacitor while activating said transfer device when said wordline is energized and said bitline is disconnected; andmeans for measuring the voltage in said capacitor to be provided to a measuring means. 13. The method of claim 12, wherein said on-chip voltage amplifier amplifies an equalized bitline and capacitor voltage when said bitline is disconnected. 14. The method of claim 13 wherein voltage signals are independently applied to said wordline and said first and second inputs to monitor the charging of said capacitor and said transfer characteristics. 15. The method of claim 12, wherein said charge transfer device and said capacitor are connected in series for monitoring and stressing the charge transfer characteristics of said charge transfer device operating in a product like environment. 16. The method of claim 15, wherein said charge transfer device and said capacitor are connected in series and independently monitor the discharging characteristics of said capacitor and the transfer characteristics of said charge transfer device. 17. The method of claim 12, wherein said measuring means is a tester.
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