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Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-029/00
출원번호 US-0338928 (2003-01-08)
발명자 / 주소
  • LaRosa, Giuseppe
  • Strong, Alvin W.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Shkurko Eugene
인용정보 피인용 횟수 : 45  인용 특허 : 1

초록

An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout me

대표청구항

1. An apparatus for measuring the transfer characteristics of a charge transfer device and the charge holding capability of a capacitor wherein said charge transfer device and said capacitor are integral to a memory cell, the apparatus comprising:a memory array consisting of a plurality of said memo

이 특허에 인용된 특허 (1)

  1. Choi Mun-Kyu,KRX ; Chung Yeon-Bae,KRX, Variable test voltage circuits and methods for ferroelectric memory devices.

이 특허를 인용한 특허 (45)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  6. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  7. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  8. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  9. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  10. Masleid,Robert P., Column select multiplexer circuit for a domino random access memory array.
  11. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  12. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  13. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  14. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  15. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  16. Suzuki, Shingo, Device aging determination circuit.
  17. Masleid, Robert P, Dynamic ring oscillators.
  18. Bansal, Aditya; Kim, Jae-Joon; Rao, Rahul M., Estimating delay deterioration due to device degradation in integrated circuits.
  19. Meyer,Russell L.; Beffa,Ray, Integrated circuit devices having reducing variable retention characteristics.
  20. Masleid, Robert P, Inverting zipper repeater circuit.
  21. Masleid, Robert P., Inverting zipper repeater circuit.
  22. Masleid, Robert Paul, Inverting zipper repeater circuit.
  23. Masleid, Robert, Leakage efficient anti-glitch filter.
  24. Borot, Bertrand; Bechet, Emmanuel, Memory including a performance test circuit.
  25. Meyer, Russell L.; Beffa, Ray, Method of reducing variable retention characteristics in DRAM cells.
  26. Anemikos, Theodoros E.; Dewey, Douglas S.; Nsame, Pascal A.; Polson, Anthony D., On-going reliability monitoring of integrated circuit chips in the field.
  27. Masleid, Robert Paul, Power efficient multiplexer.
  28. Masleid, Robert Paul, Power efficient multiplexer.
  29. Masleid, Robert Paul, Power efficient multiplexer.
  30. Masleid, Robert Paul, Power efficient multiplexer.
  31. Bickford, Jeanne P.; Goss, John R.; Habib, Nazmul; McMahon, Robert, Reliability evaluation and system fail warning methods using on chip parametric monitors.
  32. Bickford, Jeanne P.; Goss, John R.; Habib, Nazmul; McMahon, Robert, Reliability evaluation and system fail warning methods using on chip parametric monitors.
  33. Bickford, Jeanne P.; Goss, John R.; Habib, Nazmul; McMahon, Robert, Reliability evaluation and system fail warning methods using on chip parametric monitors.
  34. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  35. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  36. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  37. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  38. Masleid, Robert Paul; Sousa, Jose; Kottapalli, Venkata, Scannable dynamic circuit latch.
  39. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  40. Suzuki, Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  41. Suzuki, Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  42. Suzuki,Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  43. Suzuki,Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  44. Pitkethly, Scott; Masleid, Robert P., Triple latch flip flop system and method.
  45. Pitkethly,Scott; Masleid,Robert P., Triple latch flip flop system and method.
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