초록 ▼

A structure and method of making an NPN heterojunction bipolar transistor ( 100 ) includes a semiconductor substrate ( 11 ) with a first region ( 82 ) containing a dopant ( 86 ) for forming a base region of the transistor. A second region ( 84 ) adjacent to the first region is used to form an emitte

A structure and method of making an NPN heterojunction bipolar transistor ( 100 ) includes a semiconductor substrate ( 11 ) with a first region ( 82 ) containing a dopant ( 86 ) for forming a base region of the transistor. A second region ( 84 ) adjacent to the first region is used to form an emitter region of the transistor. An interstitial trapping material ( 81 ) reduces diffusion of dopants in the base region during subsequent thermal processing.

대표청구항 ▼

1. A high speed NPN heterojunction bipolar transistor, comprising:a semiconductor substrate having a first region containing a p-type dopant for forming a base region of the transistor; anda second region containing an n-type dopant forming an emitter region of the transistor adjacent to and over th

1. A high speed NPN heterojunction bipolar transistor, comprising:a semiconductor substrate having a first region containing a p-type dopant for forming a base region of the transistor; anda second region containing an n-type dopant forming an emitter region of the transistor adjacent to and over the first region, wherein the second region includes an interstitial trapping material. 2. The high speed NPN heterojunction bipolar transistor of claim 1, further including a dielectric material formed on the semiconductor substrate. 3. The high speed NPN heterojunction bipolar transistor of claim 2, wherein the dielectric material includes thermally grown silicon dioxide. 4. The high speed NPN heterojunction bipolar transistor of claim 2, wherein the first region is separated from the dielectric material by the second region. 5. The high speed NPN heterojunction bipolar transistor of claim 1, wherein the interstitial trapping material includes carbon. 6. The high speed NPN heterojunction bipolar transistor of claim 1, wherein the p-type dopant includes boron. 7. The high speed NPN heterojunction bipolar transistor of claim 1, wherein the first region includes silicon germanium. 8. The high speed NPN heterojunction bipolar transistor of claim 1, wherein the second region has a second dopant for forming an emitter region of the transistor. 9. The high speed NPN heterojunction bipolar transistor of claim 1, wherein the n-type dopant includes arsenic. 10. The high speed NPN heterojunction bipolar transistor of claim 1, wherein the first region includes interstitial trapping material. 11. A high speed NPN heterojunction bipolar transistor, comprising:a semiconductor substrate having a surface formed with a dielectric material;a first semiconductor layer having a n-type dopant formed adjacent to and under the dielectric material and including an interstitial trapping material; anda second semiconductor layer having a p-type dopant to form a base region of the high speed NPN heterojunction bipolar transistor. 12. The high speed NPN heterojunction bipolar transistor of claim 11, wherein the first semiconductor layer is formed over and adjacent to the second semiconductor layer. 13. The high speed NPN heterojunction bipolar transistor of claim 11 wherein the p-type dopant includes boron. 14. The high speed NPN heterojunction bipolar transistor of claim 11, wherein the interstitial trapping material includes carbon. 15. A method of forming a high speed NPN heterojunction bipolar transistor, comprising:providing a semiconductor substrate having a first region formed containing a p-type dopant for forming a base region of the transistor and a second region formed adjacent to and over the first region and comprising an interstitial trapping material. 16. The method of claim 15, further including the step of forming a dielectric material on the semiconductor substrate. 17. The method of claim 16, wherein the first region is separated from the dielectric material by the second region. 18. The method of claim 16, wherein the interstitial trapping material comprises carbon. 19. The method of claim 17, wherein the second region contains a n-type dopant to form an emitter electrode of the transistor. 20. The method of claim 19, wherein the n-type dopant includes arsenic. 21. The method of claim 15, wherein the first p-type dopant includes boron. 22. The method of claim 15, wherein the first region includes silicon germanium. 23. The method of claim 15, wherein the first region includes interstitial trapping material.