Low power apparatus and algorithm for sub-rate bit acquisition and synchronization of high speed clockless data streams
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-007/00
출원번호
US-0501801
(2000-02-09)
발명자
/ 주소
Miller, Karl Eric
Wilcox, Loran Albert
출원인 / 주소
Motorola, Inc.
대리인 / 주소
KIekotka James E.
인용정보
피인용 횟수 :
7인용 특허 :
16
초록▼
A clockless synchronizer ( 200 ) is used for sub-rate bit acquisition and synchronization of high speed clockless data streams. Clockless synchronizer ( 200 ) comprises burst detector ( 210 ), multi-phase signal generator ( 220 ), multi-phase signal router ( 230 ), multi-phase signal sampler ( 240 )
A clockless synchronizer ( 200 ) is used for sub-rate bit acquisition and synchronization of high speed clockless data streams. Clockless synchronizer ( 200 ) comprises burst detector ( 210 ), multi-phase signal generator ( 220 ), multi-phase signal router ( 230 ), multi-phase signal sampler ( 240 ), clock generator ( 250 ), correlation control circuit ( 260 ), and output data selector ( 270 ). Clockless synchronizer ( 200 ) is fabricated on a single ASIC, and it is free from the 'data rate less than the available clock' limitation.
대표청구항▼
1. A clockless synchronizer comprising:a multi-phase signal generator for providing N multiphase signals, where N is a positive integer;a multi-phase signal router coupled to said multi-phase signal generator for receiving said N multi-phase signals and sending M multi-phase signals, where M is a po
1. A clockless synchronizer comprising:a multi-phase signal generator for providing N multiphase signals, where N is a positive integer;a multi-phase signal router coupled to said multi-phase signal generator for receiving said N multi-phase signals and sending M multi-phase signals, where M is a positive integer not equal to N;a multi-phase signal sampler coupled to said multi-phase signal router for receiving said M multi-phase signals and for sending M sampled signals;a correlation control circuit coupled to said multi-phase signal router and coupled to said multi-phase signal sampler for determining a best clock correlated multi-phase signal from said M sampled signals;a timing generator coupled to said correlation control circuit, said timing generator providing timing pulses at a known rate;an output data selector coupled to said correlation control circuit and coupled to said multi-phase signal sampler for selecting said best clock correlated multi-phase signal from said M sampled signals; andsaid correlation control circuit further comprises means for inhibiting sampling circuits in said multi-phase signal sampler. 2. The clockless synchronizer as claimed in claim 1, wherein said multi-phase signal generator comprises means for providing said N multi-phase signals as signals that are phase-shifted relative to each other. 3. The clockless synchronizer as claimed in claim 2, wherein said multi-phase signal generator comprises a plurality of gates and uses gate delays for providing said N multi-phase signals. 4. The clockless synchronizer as claimed in claim 1, wherein said multi-phase signal router comprises means for routing signals at a first number of input ports to a second number of output ports. 5. The clockless synchronizer as claimed in claim 1, wherein said multi-phase signal sampler comprises at least three flip-flop circuits. 6. The clockless synchronizer as claimed in claim 1, wherein said multi-phase signal sampler comprises at least three latch circuits. 7. The clockless synchronizer as claimed in claim 1, wherein said correlation control circuit comprises means for performing binary comparisons between a number of multi-phase signals and a local clock signal from said timing generator. 8. The clockless synchronizer as claimed in claim 1, wherein said correlation control circuit comprises means for using a set of equations for performing correlations between a number of multi-phase signals and a local clock signal. 9. The clockless synchronizer as claimed in claim 1, wherein said correlation control circuit comprises a state machine for performing binary comparisons between a number of multi-phase signals and a local clock signal. 10. The clockless synchronizer as claimed in claim 1, wherein said correlation control circuit further comprises means for providing selection signals to said output data selector. 11. The clockless synchronizer as claimed in claim 1, wherein said correlation control circuit further comprises means for determining said best clock correlated multi-phase signal. 12. The clockless synchronizer as claimed in claim 11, wherein said correlation control circuit further comprises means for using a clock signal, a setup time, and a hold time for determining said best clock correlated multi-phase signal. 13. A circuit for synchronizing clockless signals, the circuit comprising:a multi-phase signal generator for providing N multiphase input signals, where N is a positive integer, and wherein the multi-phase signal generator comprises a series of gates, each gate having at least one semiconducting junction;a multi-phase signal router coupled to said multi-phase signal generator for receiving said N multi-phase input signals and for routing the N multi-phase input signals between a plurality of outputs to create M multi-phase output signals, where M is a positive integer not equal to N;a multi-phase signal sampler coupled to said multi-phase signal router and having a plurality of sampling ci rcuits, wherein the multi-phase signal sampler is configured to receive said M output multi-phase signals and to produce M sampled signals from said plurality of sampling circuits;a correlation control circuit coupled to said multi-phase signal router and to said multi-phase signal sampler for determining a best clock correlated multi-phase signal from said M sampled signals;a timing generator coupled to said correlation control circuit, said timing generator providing timing pulses at a known rate;an output data selector coupled to said correlation control circuit and coupled to said multi-phase signal sampler for selecting said best clock correlated multi-phase signal from said M sampled signals; andan inhibiting circuit configured to inhibit selected ones of said plurality of sampling circuits in said multi-phase signal sampler as a function of the best clock correlated multi-phase signal.
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이 특허에 인용된 특허 (16)
Burns Richard J. (Canoga Park CA) Grim Kenneth R. (Moorpark CA) Levy Miguel E. (Camarillo CA), Analog-digital correlator.
Georgiou Christos J. (White Plains NY) Larsen Thor A. (Hopewell Junction NY) Lee Ki W. (Yorktown Heights NY), Digital phase alignment and integrated multichannel transceiver employing same.
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