초록 ▼

A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention

A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.

대표청구항 ▼

1. An electrically erasable programmable read only memory (EEPROM) cell capable of storing a first bit and a second bit of information, said cell comprising:a semiconducting substrate of a first conductivity type;a first region comprising a portion of said semiconducting substrate doped to have a co

1. An electrically erasable programmable read only memory (EEPROM) cell capable of storing a first bit and a second bit of information, said cell comprising:a semiconducting substrate of a first conductivity type;a first region comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;a second region, spaced from said first region, comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate, a channel being formed in the space between said first region and said second region within said semiconducting substrate;a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;a nonconducting charge trapping layer formed on and overlaying said first insulating layer;a second insulating layer formed on and overlaying said nonconductive charge trapping layer;a gate comprising an electrically conductive material formed on and overlaying said second insulating layer;wherein said charge trapping layer is formed to allow first information bit programming in a first forward direction, said first information bit programming comprising electron injection into a first charge storage region of said charge trapping layer substantially directly above said channel such that first quantity of electrons is received and retained to provide said cell with a first threshold voltage greater than a first selected value when said first bit is read in said first forward direction and to provide said cell with a second threshold voltage when said first bit is read in a direction opposite said first forward direction, said first threshold voltage being sufficiently less than said second threshold voltage so as to allow said cell to store said first information bit when said first bit is read in said direction opposite said first forward direction but to not store said first information bit with the same probability of detecting said first information bit when said first bit is read in said first forward direction;wherein said charge trapping layer is formed to allow second information bit programming in a second forward direction, said information bit programming comprising electron injection into a second charge storage region of said charge trapping layer sustantially directly above said channel such that a second quantity of electrons is received and retained to provide said cell with a third threshold voltage greater than a third selected value when said second bit is read in said second forward direction and to provide said cell with a fourth threshold voltage when said second bit is read in a direction opposite said second forward direction, said third threshold voltage being sufficiently less than said fourth threshold voltage so as to allow said cell to store said second information bit when said second bit is read in said direction opposite said second forward direction but to not store said second information bit with the same probability of detecting said second information bit when said second bit is read in said second forward direction, andwherein said first and second bits are separately readable and erasable. 2. The memory cell according to claim 1, wherein the amount of charge stored in said first and said second charge storage regions for representing said first and said third binary values respectively is such that the ratio of the threshold voltage for reading in said first and said second reverse directions to the threshold voltage for reading in said first and said second forward directions is greater than ten to one. 3. The memory cell according to claim 1, wherein the amount of charge stored in said first and said second charge storage regions for representing said first and said third binary values respectively is such that the ratio of the threshold voltage for reading in said first and said second reverse directions to the threshold voltage for read ing in said first and said second forward directions is greater than five to one. 4. The memory cell according to claim 1, wherein the amount of charge stored in said first and said second charge storage regions for representing said first and said third binary values respectively is such that the ratio of the threshold voltage for reading in said first and said second reverse directions to the threshold voltage for reading in said first and said second forward directions is greater than two to one. 5. The memory cell according to claim 1, wherein the amount of charge stored in said first and said second charge storage regions for representing said first and said third binary values respectively is such that the ratio of the threshold voltage for reading in said first and said second reverse directions to the threshold voltage for reading in said first and said second forward directions is greater than one and one half to one. 6. The memory cell according to claim 1, wherein said cell is adapted:such that a lower limit for the voltage applied to said gate when reading the binary state of either said first or said second information bit is the voltage at which sufficient inversion is generated in said channel whereby a non-trapped charge state of the bit being read can be sensed and which permits read through of the bit not being read; andsuch that an upper limit for the voltage applied to said gate when reading the binary state of either said first or said second information bit is the voltage at which the voltage across a region of said channel underlying said first charge storage region is below the voltage applied to said first region when reading the state of said first information bit, and the voltage across a region of said channel underlying said second charge storage region is below the voltage applied to said second region when reading the state of said second information bit. 7. The memory cell according to claim 1:wherein said cell is adapted such that said first programming comprises applying programming voltages to said first region and said gate, and grounding said second region;wherein said cell is adapted such that reading said first information bit comprises applying reading voltages to said second region and said gate, grounding said first region, and measuring the resulting channel current;wherein said cell is adapted such that said second programming comprises applying programming voltages to said second region and said gate, and grounding said first region; andwherein said cell is adapted such that reading said second information bit comprises applying reading voltages to said first region and said gate, grounding said second region, and measuring the resulting channel current. 8. The memory cell according to claim 1, wherein said cell is adapted such that first information bit erasing comprises applying erasing voltages to said gate and said first region, and wherein said cell is adapted such that second information bit erasing comprises applying erasing voltages to said gate and said second region. 9. The memory cell according to claim 1, wherein said cell is adapted such that first information bit erasing comprises applying a first voltage on said gate and ground potential on said first region such that electrons are removed from said first charge storage region via said gate, and wherein said cell is adapted such that second information bit erasing comprises applying a second voltage on said gate and ground potential on said second region such that electrons are removed from said second charge storage region via said gate. 10. The memory cell according to claim 1, wherein said cell is adapted such that first information bit erasing comprises applying a first voltage to said gate and a second voltage to said first region such that electrons are removed from said first charge storage region via said first region, and wherein said cell is adapted such that second information bit erasing comprises applying a third voltage to said gate and a fourth voltage to said second region such that electrons are removed from said second charge storage region via said second region. 11. The memory cell according to claim 1, wherein said first and second insulating layers comprise silicon dioxide. 12. The memory cell according to claim 1, wherein said charge trapping layer comprises silicon nitride. 13. The memory cell according to claim 1, wherein said charge trapping layer comprises silicon dioxide with buried polysilicon islands. 14. The memory cell according to claim 1 wherein said charge trapping layer comprises silicon dioxide with impurities therein. 15. The memory cell according to claim 1, wherein said semiconducting substrate comprises P type semiconductor material. 16. The memory cell according to claim 1, wherein said first and said second regions comprise N+ semiconductor material. 17. An electrically erasable programmable read only memory (EEPROM) cell capable of storing a first bit and a second bit of information, said cell comprising:a semiconducting substrate of a first conductivity type;a first region comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;a second region, spaced from said first region, comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate, a channel being formed between said first region and said second region within said semiconducting substrate;a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;a non conductive charge trapping layer formed on and overlaying said first insulating layer;a second insulating layer formed on and overlaying said non conductive charge trapping layer;a gate comprising an electrically conductive material formed on and overlaying said second insulating layer;wherein said cell is adapted to allow programming comprising storing a first information bit by receiving and retaining electrons injected into said non conductive charge trapping layer in a first trapping region substantially directly above said channel to represent a first binary value and not receiving electrons in said first trapping region to represent a second binary value and storing a second information bit by receiving and retaining electrons injected into said non conductive charge trapping layer in a second trapping region close to said second region to represent a third binary value and not receiving electrons in said second trapping region to represent a fourth binary value; andwherein each said bit is adapted to be read in a direction opposite to that in which it was programmed such that a lower limit for the voltage applied to said gate during reading for either said first bit or said second bit is the voltage at which sufficient inversion is generated in said channel whereby a non-trapped charge state of the bit being read can be sensed and read through of the bit not being read is permitted, and an upper limit for the voltage applied to said gate during reading for either said first bit or said second bit is the voltage at which the voltage across a region of said channel beneath a trapped charge in said first or said second trapping region is below the voltage applied to said first region during reading for said first bit and below the voltage applied to said second region during reading for said second bit and wherein said first and second bits are separably readable and erasable. 18. The memory cell according to claim 17, wherein said cell is adapted to allow said first information bit and said second information bit to be erased by removing electrons from respective trapping regions in said non conductive charge trapping layer previously stored therein during said programming. 19. The memory cell according to claim 17:wherein said cell is adapted to have said first information bit be programmed by applying p rogramming voltages to said first region and said gate, and a reference voltage to said second region;wherein said cell is adapted to have said first information bit be read by applying reading voltages to said second region and said gate, applying said reference voltage to said first region, and measuring the resulting channel current;wherein said cell is adapted to have said second information bit be programmed by applying programming voltages to said second region and said gate, and said reference voltage to said first region; andwherein said cell is adapted to have said second information bit be read by applying reading voltages to said first region and said gate, applying said reference voltage to said second region, and measuring the resulting channel current. 20. The memory cell according to claim 19, wherein said reference voltage is ground. 21. The memory cell according to claim 17, wherein said cell is adapted to have said first information bit be erased by applying erasing voltages to said gate and said first region, and wherein said cell is adapted to have said second information bit be erased by applying erasing voltages to said gate and said second region. 22. The memory cell according to claim 17, wherein said cell is adapted to have said first information bit be erased by applying a first voltage to said gate and a reference voltage to said first region such that electrons are removed from said first trapping region via said gate, and wherein said cell is adapted to have said second information bit be erased by applying a second voltage to said gate and said reference voltage to said second region such that electrons are removed from said second trapping region via said gate. 23. The memory cell according to claim 22, wherein said reference voltage is ground. 24. The memory cell according to claim 17, wherein said cell is adapted to have said first information bit be erased by applying a first voltage to said gate and a second voltage to said first region such that electrons are removed from said first trapping region via said first region, and wherein said cell is adapted to have said second information bit be erased by applying a third voltage to said gate and a fourth voltage to said second region such that electrons are removed from said second trapping region via said second region. 25. The memory cell according to claim 17, wherein said first and second insulating layers comprise silicon dioxide. 26. The memory cell according to claim 17, wherein said charge trapping layer comprises silicon nitride. 27. The memory cell according to claim 17, wherein said charge trapping layer comprises silicon dioxide with buried polysilicon islands. 28. The memory cell according to claim 17, wherein said charge trapping layer comprises silicon dioxide with impurities therein. 29. The memory cell according to claim 17, wherein said semiconducting substrate comprises P-type semiconductor material. 30. The memory cell according to claim 17, wherein said first and said second regions comprise N+ semiconductor material. 31. A. An electrically erasable programmable read only memory (EEPROM) cell capable of storing a first bit and a second bit of information, said cell comprising:a semiconducting substrate of a first conductivity type;a first region comprising a portion of said semiconducting substrate doped to have a conductivity type opposite that of said semiconducting substrate;a second region, spaced from said first region, comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate, a channel being formed-between said first region and said second region within said semiconducting substrate;a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;a non conductive charge trapping layer formed on and overlaying said first insulating layer;a second insulating layer formed on and overlaying said non conductive ch arge trapping layer;a gate comprising an electrically conductive layer formed on and overlaying said second insulating layer;wherein said memory cell is adapted to be programmed by forming a first bit such that hot electron injection into said non conductive charge trapping layer in a first storage region substantially direct above said channel represents a first binary value and no electron injection into said first storage region represents a second binary value, and by forming a second bit such that hot electron injection into said non conductive charge trapping layer in a second storage region substantially directly above said channel represents a third binary value and no electron injection into said second storage region represents a fourth binary value;wherein each said bit is adapted to be read in a direction opposite from that in which it was programmed such that a maximum gate voltage applied to said gate during reading the binary state of either said first bit or said second bit is the voltage at which the voltage across a region of said channel underlying said first storage region is below the voltage applied to said first region when reading the state of said first bit and the voltage across a region of said channel underlying said second storage region is below the voltage applied to said second region when reading the state of said second bit; andwherein said cell is adapted to be erased by applying ground potential to said gate and removing electrons from said first storage region via said first region to erase said first bit, and removing electrons from said second storage region via said second region to erase said second bit and wherein said first and second bits are separately readable and erasable. 32. An electrically erasable programmable read only memory (EEPROM) cell capable of storing a first bit and a second bit of information, said cell comprising:a semiconducting substrate of a first conductivity type;a first region comprising a portion of said semiconducting substrate doped to have a conductivity type opposite that of said semiconducting substrate;a second region, spaced from said first region, comprising a portion of said semiconducting substrate doped to have a conductivity type opposite that of said semiconducting substrate, a channel being formed in the space between said first region and said second region within said semiconducting substrate;a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;a non conductive charge trapping layer formed on and overlaying said first insulating layer;a second insulating layer formed on and overlaying said non conductive charge trapping layer;a gate comprising an electrically conductive layer formed on and overlaying said second insulating layer;wherein said memory cell is adapted to be programmed by forming a first bit such that hot electron injection into said non conductive charge trapping layer in a first storage region substantially directly above said channel represents a first binary value and no electron injection into said first storage region represents a second binary value, and by forming a second bit such that hot electron injection into said non conductive charge trapping layer in a second storage region substantially directly above said channel represent a third binary value and no electron injection into said second storage region represents a fourth binary value;wherein each said bit is adapted to be read in a direction opposite from that in which it was programmed, said cell being adapted such that a maximum gate voltage applied to said gate during either said first bit or said second bit is the voltage at which the voltage across a region of said channel beneath a trapped charge in said first or said second storage region is below the voltage applied to said first region during reading for said first bit and below the voltage applied to said second region during reading for said second bit; a ndwherein said cell is adapted to be erased by applying a negative potential to said gate and removing electrons from said first storage region via said first region to erase said first bit, and removing electrons from said second storage region via said second region to erase said second bit and wherein said first and second bits are separately readably and erasable. 33. A semiconductor memory cell capable of storing a first bit and a second bit of information, said cell comprising:a substrate of a first conductivity type including a first region of a second conductivity type opposite said first conductivity type and a second region of said second conductivity type, said first region and second region being respectively spaced from each other by a channel region normally of said first conductivity type formed therebetween;a dielectric capable of holding an electrical charge in a first charge trapping region thereof substantially directly above said channel and in a second charge trapping region substantially directly above said channel;a conductive gate formed over said dielectric;means for programming a first bit by applying a first voltage to said first region and a second voltage to said gate, thereby to cause electrons to be lodged on and stored in said first charge trapping region so as to represent a first binary value, and for not applying said first and said second voltages so as to represent a second binary value;means for programming a second bit by applying a third voltage to said second region and said second voltage to said gate, thereby to cause electrons to be lodged on and stored in said second charge trapping region so as to represent a third binary value, and for not applying said third and said second voltages so as to represent a fourth binary value;means for applying a fourth voltage to said second region and a fifth voltage to said gate thereby to cause a current to be read indicating the presence or absence of a stored charge in said first charge trapping region representing said first or said second binary value stored in said first bit, said fifth voltage being between a sixth voltage sufficient to invert said channel with no charge in said first charge trapping region and a seventh voltage sufficient to create a voltage beneath said fourth voltage at a point in said channel beneath an edge of said first charge trapping region with charge stored therein; andmeans for applying an eighth voltage to said first region and a ninth voltage to said gate thereby to cause a current to be read indicating the presence or absence of a stored charge in said second charge trapping region representing said third or said fourth binary value stored in said second bit, said ninth voltage being between a tenth voltage sufficient to invert said channel with no charge in said second charge trapping region and an eleventh voltage sufficient to create a voltage beneath said ninth voltage at a point in said channel beneath an edge of said second charge trapping region with charge stored therein and means for separably read and erase said first and second bit. 34. The memory cell according to claim 33, wherein said dielectric further comprises:a first layer of silicon dioxide formed on said substrate;a layer of silicon nitride formed on said first layer of silicon dioxide, said layer of silicon nitride being capable of retaining charge in a first selected portion thereof to represent a binary value stored in said first bit and in a second selected portion thereof to represent a binary value stored in said second bit; anda second layer of silicon dioxide formed on said silicon nitride, said second layer of silicon dioxide formed to assist said silicon nitride in retaining charge trapped in said first and said second selected portions despite the electric fields generated therein. 35. An electrically erasable programmable read only memory (EEPROM) cell capable of storing a first bit and a second bit of information, said cell co mprising:semiconducting substrate of a first conductivity type;a first region comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;a second region, spaced from said first region, comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate, a channel being formed in the space between said first region and said second region within said semiconducting substrate;a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;a nonconducting charge trapping layer formed on and overlaying said first insulating layer;a second insulating layer formed on and overlaying said nonconducting charge trapping layer;a gate comprising an electrically conductive material formed on and overlaying said second insulating layer;wherein said charge trapping layer is formed to allow first information bit programming in a first forward direction, said first information bit programming comprising charge injection into a first charge storage region of said charge trapping layer substantially directly above said channel such that a first quantity of charge is received and retained to provide said cell with a first threshold voltage greater than a first selected value when said first bit is read in said first forward direction and to provide said cell with a second threshold voltage when said first bit is read in a direction opposite said first forward direction, said first threshold voltage being sufficiently less than said second threshold voltage so as to allow said cell to store said first information bit when said first bit is read in said direction opposite said first forward direction but to not store said first information bit with the same probability of detecting said first information bit when said first bit is read in said first forward direction;wherein said charge trapping layer is formed to allow second information bit programming in a second forward direction, said second information bit programming comprising charge injection into a second charge storage region of said charge trapping layer substantially directly above said channel such that a second quantity of charge is received and retained so as to provide said cell with a third threshold voltage greater than a third selected value when said second bit is read in said second forward direction and to provide said cell with a fourth threshold voltage when said second bit is read in a direction opposite said second forward, said third threshold voltage being sufficiently less than said fourth threshold voltage so as to allow said cell to store said second information bit when said second bit is read in said direction opposite said second forward direction but to not store said second information bit with the same probability of detecting said second information bit when said second bit is read in said second forward direction, andwherein said first and second bits are separately readable and erasable. 36. An electrically erasable programmable read only memory (EEPROM) cell capable of storing a first bit and a second bit of information, said cell comprising:a semiconducting substrate of a first conductivity type;a first region comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate;a second region, spaced from said first region, comprising a portion of said semiconducting substrate doped to have a conductivity opposite that of said semiconducting substrate, a channel being formed between said first region and said second region within said semiconducting substrate;a first insulating layer overlaying and covering said channel portion of said semiconducting substrate;a non conducting charge trapping layer formed on and overlaying said first insulating layer;a second insulating layer formed on and overlaying said non conducting charge trapping layer;a gate comprising an electrically conductive material formed on and overlaying said second insulating layer;wherein said cell is adapted to allow programming comprising receiving and retaining electrons injected into said non conducting charge trapping layer in a first trapping region substantially directly above said channel to form a first bit and in a second trapping region substantially directly above said channel to form a second bit; andwherein each said bit is adapted to be read in a direction opposite to that in which it was programmed such that a lower limit for the voltage applied to said gate during reading for either said first bit or said second bit is the voltage at which sufficient inversion is generated in said channel whereby an unprogrammed state of the bit being read can be sensed and read through of the bit not being read is permitted, and an upper limit for the voltage applied to said gate during reading for either said first bit or said second bit is the lowest voltage for which a programmed value of said first or second bit can be read without affecting the programmed/non-programmed state of said second or first bit.