Resetting a processor in an isolated execution environment
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/00
출원번호
US-0751586
(2000-12-29)
발명자
/ 주소
Ellison, Carl M.
Golliver, Roger A.
Herbert, Howard C.
Lin, Derrick C.
McKeen, Francis X.
Neiger, Gilbert
Sutton, James A.
Thakkar, Shreekant S.
Mittal, Millind
Reneris, Ken
출원인 / 주소
Intel Corporation
대리인 / 주소
Blakely, Sokoloff, Taylor & Zafman LLP
인용정보
피인용 횟수 :
12인용 특허 :
132
초록▼
A method, apparatus, and system for invoking a reset process in response to a logical processor being individually reset is disclosed. When a last logical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory is reset, it is reset without
A method, apparatus, and system for invoking a reset process in response to a logical processor being individually reset is disclosed. When a last logical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory is reset, it is reset without clearing a cleanup flag. Subsequently, an initializing physical processor invokes an initialization process that determines that the cleanup flag is set. The initialization process invokes the execution of a processor nub loader, and if the cleanup flag is set, the processor nub loader scrubs the isolated area of memory and invokes a controlled close for the initializing physical processor which clears the cleanup flag. The initializing physical processor then re-performs the initialization process. Upon the second iteration of the initialization process, with the cleanup flag not set, a new clean isolated area of memory is created for the initializing physical processor.
대표청구항▼
1. A method comprising:invoking a reset process in response to a logical processor being individually reset, the reset logical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory;determining whether the reset logical processor is a last
1. A method comprising:invoking a reset process in response to a logical processor being individually reset, the reset logical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory;determining whether the reset logical processor is a last logical processor of a physical processor and a last logical processor of the platform to be reset and if so,invoking an initialization process for an initializing physical processor;determining whether a cleanup flag is set; andif the cleanup flag is set,scrubbing the isolated area of memory. 2. The method of claim 1 wherein the initialization process for the initializing physical processor in which the cleanup flag is set further comprises clearing the cleanup flag and creating a new isolated area of memory for use by the initializing physical processor. 3. The method of claim 1 wherein if the cleanup flag is not set during the initialization process for the initializing physical processor a new isolated area of memory is created. 4. The method of claim 1 wherein the initializing physical processor utilizes the isolated area of memory associated with the reset logical processor. 5. The method of claim 1 wherein the initializing physical processor is a first physical processor to enroll in the initialization process including a first logical processor to enroll in the initialization process. 6. The method of claim 1 wherein the initializing physical processor communicates with an input/output controller hub (ICH), the ICH having isolated range values which correspond to the isolated area of memory. 7. The method of claim 1 wherein the initialization process for the initializing physical processor in which the cleanup flag is set further comprises:reading an isolated range value from an input/output controller hub (ICH) corresponding to the isolated area of memory previously associated with the reset logical processor;setting an isolated range value of the initializing physical processor to the isolated range value of the ICH; andcopying a processor nub loader into the isolated area of memory. 8. The method of claim 7 wherein the processor nub loader scrubs the isolated area of memory. 9. The method of claim 7 wherein the initializing physical processor undergoes a controlled close clearing the cleanup flag. 10. The method of claim 9 wherein the initialization process further comprises creating a new isolated area of memory for the initializing physical processor. 11. The method of claim 10 wherein creating the new isolated area of memory for the initializing physical processor comprises:setting a new isolated range value for the initializing physical processor;setting a new isolated range value in the ICH;copying the processor nub loader into the new isolated area of memory; andexecuting the processor nub loader. 12. The method of claim 11 wherein the initialization process further comprises initializing the new isolated area of memory for the platform. 13. The method of claim 11 wherein the initialization process further comprises setting the clean up flag. 14. An apparatus comprising:a physical processor to invoke a reset process in response to a logical processor being individually reset, the reset logical processor and the physical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory, the physical processor to determine whether the reset logical processor is a last logical processor of the physical processor and a last logical processor of the platform to be reset; andan initializing physical processor to invoke an initialization process if the physical processor determined that the reset logical processor was a last logical processor of the physical processor and a last logical processor of the platform to be reset, the initialization process to determine whether a cleanup flag is set; andif the cleanup flag is set,the initialization process invokes a processor nub loader to scrub the isolated area of memory. 15. The apparatus of claim 14 wherein if the cleanup flag is set the initialization process clears the cleanup flag and creates a new isolated area of memory for use by the initializing physical processor. 16. The apparatus of claim 14 wherein if the cleanup flag is not set the initialization process creates a new isolated area of memory. 17. The apparatus of claim 14 wherein the initializing physical processor utilizes the isolated area of memory associated with the reset logical processor. 18. The apparatus of claim 14 wherein the initializing physical processor is a first physical processor to enroll in the initialization process including a first logical processor to enroll in the initialization process. 19. The apparatus of claim 14 wherein the initializing physical processor communicates with an input/output controller hub (ICH), the ICH having isolated range values which correspond to the isolated area of memory. 20. The apparatus of claim 14 wherein if the cleanup flag is set the initialization process:reads an isolated range value from an input/output controller hub (ICH) corresponding to the isolated area of memory previously associated with the reset logical processor;sets an isolated range value of the initializing physical processor to the isolated range value of the ICH; andcopies a processor nub loader into the isolated area of memory. 21. The apparatus of claim 20 wherein the processor nub loader scrubs the isolated area of memory. 22. The apparatus of claim 20 wherein the initializing physical processor performs a controlled close clearing the cleanup flag. 23. The apparatus of claim 22 wherein the initialization process creates a new isolated area of memory for the initializing physical processor. 24. The apparatus of claim 23 wherein the initialization process creates the new isolated area of memory by:setting a new isolated range value within the initializing physical processor;setting a new isolated range value in the ICH;copying the processor nub loader into the new isolated area of memory; andexecuting the processor nub loader. 25. The apparatus of claim 24 wherein the new isolated area of memory is initialized for the platform. 26. The apparatus of claim 24 wherein the clean up flag is set. 27. A computer program product comprising:a machine readable medium having computer code stored therein, the computer program product comprising:computer readable program code for invoking a reset process in response to a logical processor being individually reset, the reset logical processor operating within a platform in an isolated execution mode and associated with an isolated area of memory;computer readable program code for determining whether the reset logical processor is a last logical processor of the platform to be reset and if so,computer readable program code for invoking an initialization process for an initializing physical processor;computer readable program code for determining whether a cleanup flag is set; andif the cleanup flag is set,scrubbing the isolated area of memory. 28. The computer program product of claim 27 wherein the computer readable program code for performing the initialization process for the initializing physical processor, when the cleanup flag is set, further comprises:computer readable program code for clearing the cleanup flag; andcomputer readable program code for creating a new isolated area of memory for use by the initializing physical processor. 29. The computer program product of claim 27 wherein the computer readable program code for performing the initialization process for the initializing physical processor, when the cleanup flag is not set, further comprises computer readable program code for creating a new isolated area of memory. 30. The computer program product of claim 27 further comprising computer readable program code for allowing the initializing physical processor to utilize the isolated area of memory associate d with the reset logical processor. 31. The computer program product of claim 27 wherein the initializing physical processor is a first physical processor to enroll in the initialization process including a first logical processor to enroll in the initialization process. 32. The computer program product of claim 27 further comprising computer readable program code for allowing the initializing physical processor to communicate with an input/output controller hub (ICH), the ICH having isolated range values which correspond to the isolated area of memory. 33. The computer program product of claim 27 wherein the computer readable program code for performing the initialization process for the initializing physical processor, when the cleanup flag is set, further comprises:computer readable program code for reading an isolated range value from an input/output controller hub (ICH) corresponding to the isolated area of memory previously associated with the reset logical processor;computer readable program code for setting an isolated range value of the initializing physical processor to the isolated range value of the ICH; andcomputer readable program code for copying a processor nub loader into the isolated area of memory. 34. The computer program product of claim 33 further comprising computer readable program code for allowing the processor nub loader to scrub the isolated area of memory. 35. The computer program product of claim 33 further comprising computer readable program code for performing a controlled close upon the initializing physical processor and clearing the cleanup flag. 36. The computer program product of claim 35 wherein the computer readable program code for initializing the initializing physical processor further comprises computer readable program code for creating a new isolated area of memory for the initializing physical processor. 37. The computer program product of claim 36 wherein the computer readable program code for creating the new isolated area of memory for the initializing physical processor further comprises:computer readable program code for setting a new isolated range value for the initializing physical processor;computer readable program code for setting a new isolated range value in the ICH;computer readable program code for copying the processor nub loader into the new isolated area of memory; andcomputer readable program code for executing the processor nub loader. 38. The computer program product of claim 37 further comprising computer readable program code for initializing the new isolated area of memory for the platform. 39. The computer program product of claim 37 further comprising computer readable program code for setting the clean up flag. 40. A system comprising:a chipset;a memory coupled to the chipset having an isolated area of memory;a physical processor coupled to the chipset and the memory operating in a platform, the physical processor to invoke a reset process in response to a logical processor being individually reset, the reset logical processor and the physical processor operating within the platform in an isolated execution mode and associated with an isolated area of memory, the physical processor to determine whether the reset logical processor is a last logical processor of the physical processor and a last logical processor of the platform to be reset; andan initializing physical processor to invokes an initialization process if the physical processor determined that the reset logical processor was a last logical processor of the physical processor and a last logical processor of the platform to be reset, the initialization process to determine whether a cleanup flag is set; andif the cleanup flag is set,the initialization process invokes a processor nub loader to scrub the isolated area of memory. 41. The system of claim 40 wherein if the cleanup flag is set the initialization process clears the cleanup flag and creates a new isolated area of memory for use by the i nitializing physical processor. 42. The system of claim 40 wherein if the cleanup flag is not set the initialization process creates a new isolated area of memory. 43. The system of claim 40 wherein the initializing physical processor utilizes the isolated area of memory associated with the reset logical processor. 44. The system of claim 40 wherein the initializing physical processor is a first physical processor to enroll in the initialization process including a first logical processor to enroll in the initialization process.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (132)
Hatada Minoru (Ebina JPX) Ishida Hideaki (Kawasaki JPX) Matsushita Masatoshi (Kawasaki JPX), Access control method for multiprocessor systems.
Gannon Patrick M. (Poughkeepsie NY) Gum Peter H. (Poughkeepsie NY) Hough Roger E. (Highland NY) Murray Robert E. (Woodstock NY), Apparatus and method for TLB purge reduction in a multi-level machine system.
Bealkowski Richard (Delray Beach FL) Blackledge ; Jr. John W. (Boca Raton FL) Cronk Doyle S. (Boca Raton FL) Dayan Richard A. (Boca Raton FL) Dixon Jerry D. (Boca Raton FL) Kinnear Scott G. (Boca Rat, Apparatus and method for preventing unauthorized access to BIOS in a personal computer system.
Heller Andrew R. (Morgan Hill CA) Worley ; Jr. William S. (Endicott NY), Authorization mechanism for transfer of program control or data between different address spaces having different storag.
Ermolovich Thomas R. (Lexington MA) Stewart Robert E. (Stow MA) Leonard Judson S. (Acton MA) Cutler David N. (Nashua NH), Communications device for data processing system.
Satou Mitsugu,JPX ; Iwata Shunichi,JPX, Computer system and semiconductor device on one chip including a memory and central processing unit for making interlock access to the memory.
Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Controlling access to multiple memory zones in an isolated execution environment.
Morley Richard E. (Greenville NH), Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and met.
Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Executing isolated mode instructions in a secure system running in privilege rings.
Nakamura Kouji,JPX, Exposure apparatus, output control method for energy source, laser device using the control method, and method of producing microdevice.
Adams Phillip M. (Parowan UT) Holmstron Larry W. (Salt Lake City UT) Jacob Steve A. (South Weber UT) Powell Steven H. (Ogden UT) Condie Robert F. (Tuscon AZ) Culley Martin L. (Tuscon AZ), Kernels, description tables, and device drivers.
Barnett Philip C.,GBX, Memory management method and apparatus for partitioning homogeneous memory and restricting access of installed applications to predetermined memory ranges.
Chemin Francois (Plaisir FRX) Ugon Michel (Maurepas FRX), Method and apparatus for certifying services obtained using a portable carrier such as a memory card.
Harold L. McFarland ; David R. Stiles ; Korbin S. Van Dyke ; Shrenik Mehta ; John Gregory Favor ; Dale R. Greenley ; Robert A. Cargnoni, Method and apparatus for debugging an integrated circuit.
Miller David A. ; Jansen Kenneth A. ; Culley Paul R. ; Taylor Mark ; Izquierdo Javier F., Method and apparatus for independently resetting processors and cache controllers in multiple processor systems.
Cotichini Christian,CAX ; Cain Fraser,CAX ; Ashworth David G.,CAX ; Livingston Peter Michael Bruce,CAX ; Solymar Gabor,CAX ; Gardner Philip B.,CAX ; Woinoski Timothy S.,CAX, Method and apparatus to monitor and locate an electronic device using a secured intelligent agent.
Kahle James Allan ; Loper Albert J. ; Mallick Soummya ; Ogden Aubrey Deene ; Sell John Victor, Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions w.
Hazard Michel (Mareil/Mauldre FRX) Ugon Michel (Maurepas FRX), Method for authenticating an external authorizing datum by a portable object, such as a memory card.
Melo Michael D. (Billerica MA), Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 8048.
Hazard Michel (Mareil/Mauldre FRX), Method for certifying the authenticity of a datum exchanged between two devices connected locally or remotely by a trans.
Ugon Michel (Maurepas FRX) Oisel Andr (Elancourt FRX), Method for checking the integrity of a program or data, and apparatus for implementing this method.
Ganapathy Narayanan ; Stevens Luis F. ; Schimmel Curt F., Method, system and computer program product for dynamically allocating large memory pages of different sizes.
Eugene Feng ; Gary Phillips, Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space.
Grimmer ; Jr. George G. ; Rhoades Michael W., Microcontroller with security logic circuit which prevents reading of internal memory by external program.
Goetz John W. ; Mahin Stephen W. ; Bergkvist John J., Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set archi.
Blomgren James S. (San Jose CA) Bracking Jimmy (San Jose CA) Richter David (San Jose CA) Spahn Francis (El Cerrito CA), Microprocessor with operation capture facility.
Reardon David C., Network security system allowing access and modification to a security subsystem after initial installation when a master token is in place.
Provanzano Salvatore R. (Melrose MA) Aldrich Wilbert H. (Winchester MA) D\Angelo Robert A. (Windham NH) Drottar Emil P. (Ipswich MA) Finnegan ; Jr. John J. (Hudson NH) Heom James (Bedford MA) Hill La, Programmable controller.
Robinson Paul T. (Arlington MA) Mason Andrew H. (Hollis NH) Hall Judith S. (Sudbury MA), Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces.
John K. Gee ; David A. Greve ; David S. Hardin ; Allen P. Mass ; Michael H. Masters ; Nick M. Mykris ; Matthew M. Wilding, Real time processor capable of concurrently running multiple independent JAVA machines.
Goire Christian (Les Clayes Sous Bois FRX) Sigaud Alain (Elancourt FRX) Moyal Eric (Paris FRX), Safeguarded remote loading of service programs by authorizing loading in protected memory zones in a terminal.
Browne Hendrik A., Secure computer system and method of providing secure access to a computer system including a stand alone switch operable to inhibit data corruption on a storage device.
Mark J. Foster ; Saifuddin T. Fakhruddin ; James L. Walker ; Matthew B. Mendelow ; Jiming Sun ; Rodman S. Brahman ; Michael P. Krau ; Brian D. Willoughby ; Michael D. Maddix ; Steven L. Belt, Suspend/resume capability for a protected mode microprocesser.
Hudson Jerome D. ; Champagne Jean-Paul,FRX ; Galindo Mary A. ; Hickerson Cynthia M. K. ; Hickman Donna R. ; Lockhart Robert P. ; Saddler Nancy B. ; Stange Patricia A., System and method for accessing enterprise-wide resources by presenting to the resource a temporary credential.
Angelo Michael F. ; Olarig Sompong P. ; Wooten David R. ; Driscoll Dan J., System and method for performing secure device communications in a peer-to-peer bus architecture.
Inoue Taro (Sagamihara JPX) Umeno Hidenori (Kanagawa JPX) Tanaka Shunji (Sagamihara JPX) Yamamoto Tadashi (Kanagawa JPX) Ohtsuki Toru (Hadano JPX), System for recovery from a virtual machine monitor failure with a continuous guest dispatched to a nonguest mode.
Nardone Joseph M. ; Mangold Richard P. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant methods and apparatus.
Nardone Joseph M. ; Mangold Richard T. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant methods and apparatus.
Nardone Joseph M. ; Mangold Richard P. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant player for scrambled contents.
Mason Andrew H. (Hollis NH) Hall Judith S. (Sudbury MA) Robinson Paul T. (Arlington MA) Witek Richard T. (Littleton MA), Translation buffer for virtual machines with address space match.
Scott W. Devine ; Edouard Bugnion ; Mendel Rosenblum, Virtualization system including a virtual machine monitor for a computer with a segmented architecture.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.