[특허]Digital image sensor with on -chip programmable logic

Pixim, Inc.

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Digital image sensor with on -chip programmable logic

국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H04N-005/228 H04N-005/335 H04N-003/14 H01L-027/00
미국특허분류(USC)	348/222.1; 348/294; 348/308; 250/208.1
출원번호	US-0665523 (2000-09-19)
발명자 / 주소	Deng, Zhonghan John Yang, David Xiao Dong Ewedemi, Odutola Oluseye
출원인 / 주소	Pixim, Inc.
대리인 / 주소	Beyer Weaver & Thomas, LLP
인용정보	피인용 횟수 : 74 인용 특허 : 7

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An image sensor, including a substrate having formed thereon by a CMOS process a digital sensor array having a plurality of digital pixel sensors which output analog signals corresponding to a desired image. The digital sensor array further includes supporting circuitry for converting the analog signals produced by the digital pixel sensors to digital signals corresponding to the desired image. Filter circuitry, for converting the digital signals to digital values representative of the light intensity impinging upon the plurality of digital pixel sensors, is also formed on the substrate using CMOS fabrication processes. Memory devices, including a data memory, a threshold memory, and a time index memory are formed on the substrate using CMOS fabrication techniques. A clock circuit is also formed on the substrate using CMOS fabrication processes. Programmable logic structures are formed on the substrate using CMOS fabrication processes. The programmable logic structure can be configured into a variety of circuitry or routing so as to facilitate customization or specialization of the image sensor.

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1. An image sensor, comprising:a substrate having formed thereon a digital sensor array;the digital sensor array having a plurality of digital pixel elements, each comprising a photosensor and an analog-to-digital conversation circuit, the photosensor producing an analog signal when the image sensor is exposed to light, the analog-to-digital conversation circuit receiving the analog signal and generating a digital representation thereof;the substrate having formed thereon at least one programmable logic structure programmable externally to control operations of the digital sensor array so that the digital representation can be output from the image sensor as desired; andat least one memory formed on the substrate, wherein the at least one memory includes a data memory for storing digital signal information; anda threshold memory for storing threshold values for the digital signal information. 2. The image sensor of claim 1 further including at least one memory formed on the substrate, the at least one memory for receiving said digital representation. 3. The image sensor of claim 1 wherein the digital sensor array, an at least one memory, and the at least one programmable logic structure are each formed on the substrate using CMOS fabrication techniques. 4. The image sensor of claim 3 wherein the at least one programmable logic structure includes the at least one memory. 5. The image sensor of claim 3 wherein the at least one programmable logic structure is selected from the group consisting of Simple Programmable Logic Devices, Complex Programmable Logic Devices, Field Programmable Gate Arrays, and Field Programmable Interconnect Devices. 6. The image sensor of claim 3 wherein the at least one programmable logic structure is configured to adjust pixel resolution of the image sensor. 7. The image sensor of claim 3 wherein the at least one programmable logic structure is configured to adjust bit precision of the plurality of digital pixel sensors of the digital sensor array. 8. The image sensor of claim 3 wherein the at least one programmable logic structure is programmed to adjust the resolution of the digital sensor array. 9. The image sensor of claim 3 wherein the at least one programmable logic structure is programmed to increase the processing speed of images detected with the digital sensor array. 10. The image sensor of claim 3 wherein the at least one programmable logic structure is programmable to accommodate customer specified functions. 11. An image sensor comprising:a substrate having formed thereon a digital sensor array wherein the digital sensor array is formed using a CMOS fabrication process;the digital sensor array including a plurality of light sensitive digital pixel sensors which output analog signals corresponding to an image and having supporting circuitry for converting the analog signals to digital signals corresponding to the image;decoder circuitry which receives the digital signals from the digital sensor array and converts the digital signals to digital values representative of the light intensity impinging upon the plurality of light sensitive digital pixel sensors, the decoder circuitry being formed on the substrate using a CMOS fabrication process;a plurality of filters which receive the digital values from the decoder and from an at least one memory, the at least one memory being formed on the substrate using a CMOS fabrication process;the at least one memory for storing the digital values provided by the filters, the at least one memory being formed on the substrate using a CMOS fabrication process;a control circuit which selectively transfers the digital values from the plurality of filters to memory addresses within the at least one memory, the control circuit being formed on the substrate using a CMOS fabrication process; andat least one programmable logic structure being formed on the substrate using a CMOS fabrication process. 12. The image sensor as in claim 11 wherein the at least one me mory includes a data memory for storing the digital values, a threshold memory for storing threshold values for the digital values, and a time index memory for storing different time indexed values of the digital values. 13. The image sensor of claim 12 wherein the at least one programmable logic structure is selected from the group consisting of Simple Programmable Logic Devices, Complex Programmable Logic Devices, Field Programmable Gate Arrays, and Field Programmable Interconnect Devices. 14. The image sensor of claim 13 wherein the at least one programmable logic structure is configured to adjust pixel resolution of the image sensor. 15. The image sensor of claim 13 wherein the at least one programmable logic structure is configured to adjust bit precision of the plurality of digital pixel sensors of the digital sensor array. 16. The image sensor of claim 13 wherein the at least one programmable logic structure is configured to operate as a memory controller. 17. The image sensor of claim 13 wherein the at least one programmable logic structure is programmed to adjust the dynamic range of the digital sensor array. 18. The image sensor of claim 13 wherein the at least one programmable logic structure is programmed to adjust the resolution of the digital sensor array. 19. The image sensor of claim 13 wherein the at least one programmable logic structure is programmed to increase the processing speed of images detected with the digital sensor array. 20. The image sensor of claim 13 wherein the at least one programmable logic structure is programmed to accommodate customer specified functions. 21. The image sensor of claim 11 wherein the digital sensor array is configured so that each of the plurality of light sensitive digital pixel sensors which output analog signals corresponding to an image comprises a photosensor and the supporting circuitry for converting the analog signals to digital signals includes an analog-to-digital conversation circuit for each photosensor wherein the photosensor produces an analog signal when the image sensor is exposed to light, the analog-to-digital conversation circuits receiving the analog signals and generating a digital representation corresponding to the image. 22. An image sensor, comprising:a substrate having formed thereon:a digital sensor array having a plurality of digital pixel elements, each comprising a photosensor and an analog-to-digital conversation circuit, wherein the photosensor is configured to produce an analog signal when the image sensor is exposed to light, and wherein the analog-to-digital conversation circuit uses the analog signal to generate a digital representation thereof;at least one programmable logic structure capable of being externally programmable to control operations of the digital sensor array so that the digital representation can be output from the image sensor as desired; andat least one memory including:a data memory for storing the digital signal information; anda threshold memory for storing threshold values for the digital signal information. 23. The image sensor of claim 22 wherein clock circuitry is formed on the substrate and the at least one memory further includes a time index memory for storing different time indexed values of the digital signal information. 24. The image sensor of claim 23 wherein the at least one programmable logic structure is configured to operate as a memory controller. 25. The image sensor of claim 23 wherein the at least one programmable logic structure is programmed to provide timing control to be used in conjunction with the memory. 26. The image sensor of claim 22 wherein the at least one programmable logic structure is programmed to adjust the dynamic range of the digital sensor array. 27. The image sensor of claim 23 wherein the at least one programmable logic structure is programmed to adjust the resolution of the digital sensor array. 28. The image sensor of claim 23 wherein the at least one programmable logic st ructure is programmed to increase the processing speed of images detected with the digital sensor array. 29. The image sensor of claim 21 wherein the digital sensor array, the at least one memory, and the at least one programmable logic structure are each formed on the substrate using CMOS fabrication techniques. 30. An image sensor comprising:a substrate having formed thereon a digital sensor array;the digital sensor array including a plurality of light sensitive digital pixel sensors which output analog signals corresponding to an image and having supporting circuitry for converting the analog signals to digital signals corresponding to the image;decoder circuitry which receives the digital signals from the digital sensor array and converts the digital signals to digital values representative of the light intensity impinging upon the plurality of light sensitive digital pixel sensors;a plurality of filters which receive the digital values from the decoder and from an at least one memory;the at least one memory for storing the digital values provided by the filters;a control circuit which selectively transfers the digital values from the plurality of filters to memory addresses within the at least one memory; andat least one programmable logic structure being formed on the substrate. 31. The image sensor as in claim 30 wherein the at least one memory includes a data memory for storing the digital values, a threshold memory for storing threshold values for the digital values, and a time index memory for storing different time indexed values of the digital values. 32. The image sensor of claim 31 wherein the at least one programmable logic structure is selected from the group consisting of Simple Programmable Logic Devices, Complex Programmable Logic Devices, Field Programmable Gate Arrays, and Field Programmable Interconnect Devices. 33. The image sensor of claim 32 wherein the at least one programmable logic structure is configured to adjust pixel resolution of the image sensor. 34. The image sensor of claim 32 wherein the at least one programmable logic structure is configured to adjust bit precision of the plurality of digital pixel sensors of the digital sensor array. 35. The image sensor of claim 32 wherein the at least one programmable logic structure is configured to operate as a memory controller. 36. The image sensor of claim 32 wherein the at least one programmable logic structure is programmed to adjust the dynamic range of the digital sensor array. 37. The image sensor of claim 32 wherein the at least one programmable logic structure is programmed to adjust the processing speed of images detected with the digital sensor array. 38. The image sensor of claim 32 wherein the at least one programmable logic structure is programmed to accommodate customer specified functions.

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