IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0388267
(1999-09-01)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
65 인용 특허 :
15 |
초록
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In a CDMA data communication system capable of variable rate transmission, utilization of beamforming techniques decreases the average interference caused by transmissions of a base station to subscriber stations in neighboring cells. Base stations utilize multiple transmit antennas, each transmitti
In a CDMA data communication system capable of variable rate transmission, utilization of beamforming techniques decreases the average interference caused by transmissions of a base station to subscriber stations in neighboring cells. Base stations utilize multiple transmit antennas, each transmitting signals at controlled phases, to form transmit signal beams corresponding to individual subscriber stations. Data and reference signals are transmitted along beams that change according to fixed time slots and sub-slots in order to maximize carrier-to-interference ratios (C/I) measured at subscriber stations.
대표청구항
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1. An apparatus for transmitting a wireless signal comprising:a) at least two antenna transmission subsystems, each antenna transmission subsystem further comprising:1) means for generating a phase-controlled upconverted signal based on one of a plurality of phase control signals;2) amplifier, opera
1. An apparatus for transmitting a wireless signal comprising:a) at least two antenna transmission subsystems, each antenna transmission subsystem further comprising:1) means for generating a phase-controlled upconverted signal based on one of a plurality of phase control signals;2) amplifier, operably coupled to said means for generating, for amplifying said phase-controlled upconverted signal to produce an amplified signal; and3) transmit antenna, operably coupled to said amplifier, for sending said amplified signal through the air; andb) beamforming control processor for generating each of said plurality of phase control signals, wherein each of said phase control signals is based on a signal which is time-division-multiplexed, and providing said phase control signals to each of said at least one antenna transmission subsystem, slot timing generator, operably coupled with said beamforming control processor, for generating a slot timing signal and providing said slot timing signal to said beamforming control processor, and wherein said beamforming control processor varies said phase control signals based on said slot timing signal. 2. The apparatus of claim 1 wherein said beamforming control processor is further for storing a database of beamforming parameters corresponding to a plurality of subscriber stations, wherein said beamforming control processor generates said phase control signals based on a destination subscriber station for said amplified signal. 3. The apparatus of claim 2 wherein said beamforming control processor further provides an amplitude control signal to each of said means for generating based on said destination subscriber station, wherein each of said means for generating adjusts the amplitude of said phase-controlled upconverted signal based on said amplitude control signal. 4. The apparatus of claim 2 wherein said beamforming control processor is operably coupled to said amplifier of each of said antenna transmission subsystems, for providing an amplitude control signal to each of said amplifiers based on the contents of said database, wherein said amplifier adjusts the amplitude of said amplified signal based on said amplitude control signal. 5. The apparatus of claim 1 further comprising:slot timing generator, operably coupled with said beamforming control processor, for generating a slot timing signal indicating a plurality of consecutive time slots, each said time slot comprising a data rate control (DRC) reference burst sub-slot and a data pilot burst sub-slot, and providing said slot timing signal to said beamforming control processor, wherein said beamforming control processor varies said phase control signals based on said DRC reference burst sub-slot and said data pilot burst sub-slot. 6. The apparatus of claim 1, wherein each of said means for generating a phase-controlled upconverted signal further comprises:phase-controlled digital oscillator, operably coupled with said beamforming control processor, for receiving said phase control signal and producing a phase-controlled digital mixing signal based on said phase control signal; anddigital mixer, operably coupled with said phase-controlled digital oscillator, for mixing a digital data signal with said phase-controlled digital mixing signal to produce said phase-controlled upconverted signal. 7. The apparatus of claim 6 wherein said phase-controlled digital oscillator is a phase-controlled direct digital synthesizer (DDS). 8. The apparatus of claim 1, wherein each of said means for generating a phase-controlled upconverted signal further comprises:first phase-controlled digital oscillator, operably coupled with said beamforming control processor, for receiving said phase control signal and producing first phase-controlled digital mixing signal having a phase offset based on said phase control signal;second phase-controlled digital oscillator, operably coupled with said beamforming control processor, for receiving said phase control signal and producing second phase-controlled digital mixing signal having phase offset based on said phase control signal, wherein said second phase-controlled digital mixing signal is 90 degrees out of phase with said first phase-controlled digital mixing signal;first digital mixer, operably coupled with said first phase-controlled digital oscillator, for mixing a first digital data signal with said first phase-controlled digital mixing signal to produce a first upconverted digital signal;second digital mixer, operably coupled with said second phase-controlled digital oscillator, for mixing a second digital data signal with said second phase-controlled digital mixing signal to produce a second upconverted digital signal; anddigital summer, operably connected to said first and second digital mixers, for adding said first upconverted digital signal and second upconverted digital signal to produce said phase-controlled upconverted signal. 9. The apparatus of claim 8 wherein said first phase-controlled digital oscillator and said second phase-controlled digital oscillator are phase-controlled direct digital synthesizers (DDS). 10. The apparatus of claim 8 further comprising:pseudonoise (PN) spreader, operably coupled to said first digital mixer and said second digital mixer,for receiving an in-phase digital baseband signal and an in-phase PN signal and multiplying said in-phase digital baseband signal by said in-phase PN signal to produce said first digital data signal,and for receiving a quadrature-phase baseband digital signal and a quadrature-phase PN signal and multiplying said quadrature-phase digital baseband signal by said quadrature-phase PN signal to produce said second digital data signal. 11. The apparatus of claim 8 further comprising:complex pseudonoise (PN) spreader, operably coupled to said first digital mixer and said second digital mixer, for receiving in-phase and quadrature-phase components of a data stream, and performing complex PN spreading of said in-phase and quadrature-phase components of a data stream based on in-phase and quadrature-phase short PN spreading codes, to produce said first digital data signal and said second digital data signal. 12. The apparatus of claim 11 further comprising:first baseband finite impulse response (FIR) filter, disposed between said complex PN spreader and said first digital mixer, for shaping the waveform of said first digital data signal; andsecond baseband FIR filter, disposed between said complex PN spreader and said second digital mixer, for shaping the waveform of said second digital data signal. 13. The apparatus of claim 12 further comprising:pseudonoise (PN) generator for generating in-phase and quadrature-phase samples of a PN code; andPN despreader, operably coupled to said PN generator and to reference burst chip energy means and means for measuring average received energy, for receiving digital samples and performing PN despreading of said digital samples based on said in-phase and quadrature-phase samples to produce in-phase PN despread samples and quadrature-phase PN despread samples. 14. The apparatus of claim 13 wherein said means for estimating comprises:first accumulator, operably connected to said slot timing controller and said PN despreader, for accumulating said in-phase PN despread samples received during said reference burst sub-slot indicated by said timing signals to produce an accumulated in-phase reference energy total;second accumulator, operably connected to said slot timing controller and said PN despreader, for accumulating said quadrature-phase PN despread samples received during said reference burst sub-slot indicated by said timing signals to produce an accumulated quadrature-phase reference energy total; andabsolute value module, operably connected to said first and second accumulator, for squaring said in-phase reference energy total to produce a squared in-phase reference energy total and for squaring said quadrature-phase reference energy total to produce a squared quadrature-phase reference energy total and adding said squared in-phase reference energy total to said squared quadrature-phase reference energy total to produce said reference signal energy-per-chip. 15. The apparatus of claim 14 wherein said predetermined number of samples is 96. 16. The apparatus of claim 13 wherein said means for measuring average received energy comprises:absolute value module, operably connected to said PN despreader, for calculating a sum-of-squares of each pair of despread samples consisting of one of said in-phase PN despread samples and one of said quadrature-phase PN despread samples, to produce-a stream of sum-of-squares samples; andaccumulator, operably connected to said absolute value module and said slot timing controller, for accumulating said sum-of-squares samples received during said reference burst sub-slot, to produce said average received energy per chip. 17. The apparatus of claim 16 wherein said accumulator further divides said accumulated sum-of-squares samples received during said sub-slot by a predetermined number of samples in each said sub-slot. 18. The apparatus of claim 17 wherein said predetermined number of samples is 96. 19. An apparatus for transmitting a wireless signal comprising:a) slot timing generator, for generating a slot timing signal, said slot timing signal dividing time into time slots and sub-slots, wherein each of said slots comprises at least two sub-slots;b) beamforming control processor, operably coupled with said slot timing generator, for generating a plurality of transmit phase control signals wherein each of said phase control signals remains approximately constant within each of said at least two sub-slots; andc) a predetermined number of antenna transmission subsystems, each antenna transmission subsystem further comprising:c.1) means for generating a phase-controlled amplified signal, operably coupled with said beamforming control processor, for generating a phase-controlled amplified signal having a phase based on one of said plurality of transmit phase control signals; andc.2) transmit antenna, operably coupled to said means for generating,wherein, slot timing generator, operably coupled with said beamforming control processor, for generating said slot timing signal and providing said slot timing signal to said beamforming control processor, and wherein said beamforming control processor varies said phase control signals based on said slot timing signal. 20. The apparatus of claim 19 wherein each of said time slots has a fixed time slot duration. 21. The apparatus of claim 20 wherein said fixed time slot duration is equal to 1024 chips. 22. The apparatus of claim 20 wherein one of said at least two sub-slots is a data rate control (DRC) reference burst sub-slot having a fixed time offset from the beginning of each time slot, and having a fixed DRC reference burst duration. 23. The apparatus of claim 22 wherein said fixed DRC reference burst duration is 96 chips. 24. The apparatus of claim 22 wherein each of said time slots further comprises one or more data pilot burst sub-slots having a fixed data pilot burst sub-slot length. 25. The apparatus of claim 24 wherein fixed data pilot burst sub-slot length is equal to said fixed DRC reference burst duration is 96 chips. 26. The apparatus of claim 25 wherein said one or more data pilot burst sub-slots are later in each of said time slots than said fixed DRC reference burst sub-slot. 27. The apparatus of claim 19 wherein said beamforming control processor further provides an amplitude control signal to each of said means for generating, and wherein the amplitude of said phase-controlled amplified signal varies based on said amplitude control signal. 28. The apparatus of claim 19 wherein each of said means for generating a phase-controlled amplified signal further comprises:phase-controlled digital oscillator, operably coupled with said beamforming control processor, for receiving said phase control signal and producing a phase-controlled digital mixing signal based on said phase control signal;digital mixer, operably coupled with said phase-controlled digital oscillator, for mixing a digital data signal with said phase-controlled digital mixing signal to produce an upconverted digital signal; andamplifier, operably coupled with said DAC, for amplifying said phase-controlled upconverted signal to produce said phase-controlled amplified signal. 29. The apparatus of claim 28 wherein said phase-controlled digital oscillator is a phase-controlled direct digital synthesizer (DDS). 30. The apparatus of claim 28 wherein each of said means for generating a phase-controlled amplified signal further comprises:first and second phase-controlled digital oscillators, operably coupled with said beamforming control processor, for receiving said phase control signal and producing first and second phase-controlled digital mixing signals based on said phase control signal, wherein said second phase-controlled digital mixing signal is 90 degrees out of phase with said first phase-controlled digital mixing signal;first digital mixer, operably coupled with said first phase-controlled digital oscillator, for mixing a first digital data signal with said first phase-controlled digital mixing signal to produce a first upconverted digital signal;second digital mixer, operably coupled with said second phase-controlled digital oscillator, for mixing a second digital data signal with said second phase-controlled digital mixing signal to produce a second upconverted digital signal;digital summer, operably connected to said first and second digital mixers, for adding said first upconverted digital signal and second upconverted digital signal to produce a phase-controlled upconverted signal. 31. The apparatus of claim 30 wherein said first phase-controlled digital oscillator and said second phase-controlled digital oscillator are phase-controlled direct digital synthesizers (DDS). 32. The apparatus of claim 30 further comprising:pseudonoise (PN) spreader, operably coupled to said first digital mixer and said second digital mixer,for receiving an in-phase digital baseband signal and an in-phase PN signal and multiplying said in-phase digital baseband signal by said in-phase PN signal to produce said first digital data signal,and for receiving a quadrature-phase baseband digital signal and a quadrature-phase PN signal and multiplying said quadrature-phase digital baseband signal by said quadrature-phase PN signal to produce said second digital data signal. 33. The apparatus of claim 30 further comprising:complex pseudonoise (PN) spreader, operably coupled to said first digital mixer and said second digital mixer, for receiving in-phase and quadrature-phase components of a complex data stream and in-phase and quadrature-phase short PN spreading codes, and performing complex PN spreading of said complex data stream based on said in-phase and quadrature-phase short PN spreading codes, to produce said first digital data signal and said second digital data signal. 34. The apparatus of claim 33 further comprising:first baseband finite impulse response (FIR) filter, disposed between said complex PN spreader and said first digital mixer, for shaping the waveform of said first digital data signal; andsecond baseband FIR filter, disposed between said complex PN spreader and said second digital mixer, for shaping the waveform of said second digital data signal. 35. The apparatus of claim 19 wherein said predetermined number is two.
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