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A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the inte

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG-or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

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1. An integrated circuit comprising:an interface for communicating information to an external device, the interface having an output buffer configured to store a plurality of data bits representing an output data message, the interface providing an indication to the external device that the data mes

1. An integrated circuit comprising:an interface for communicating information to an external device, the interface having an output buffer configured to store a plurality of data bits representing an output data message, the interface providing an indication to the external device that the data message is available to be transmitted to the external device;wherein the interface provides a register polled by the external device, the register containing a status bit indicating whether the output data message is in the output buffer. 2. The integrated circuit according to claim 1, wherein the register is a shift register having at least one output operatively coupled to the external device, the shift register shifting the plurality of status bits to the external device over the at least one output. 3. The integrated circuit according to claim 2, wherein the plurality of status bits am located closest to a transmission end of the shift register. 4. The integrated circuit according to claim 3, wherein the external system is configured to poll only the plurality of status bits to determine if the data message is available to be transmitted. 5. The integrated circuit according to claim 4, wherein the external device shifts a plurality of status bits into the shift register indicating whether a data message is in an output buffer associated with the external device. 6. The integrated circuit according to claim 5, wherein the status bits indicate that there is no message in the output buffer associated with the external device. 7. The integrated circuit according to claim 6, wherein the external device simultaneously shifts the plurality of status bits into the shift register indicating whether a data message is in the output buffer associated with the external device while polling the plurality of status bits indicating whether a data message is in the output buffer of the integrated circuit. 8. The integrated circuit according to claim 3, wherein at least one of the plurality of status bits indicates whether the integrated circuit can accept an input message and wherein the external system is configured to poll only, the plurality of status bits. 9. The integrated circuit according to claim 3, wherein the shift register has at least one data input from the external device, the external device being adapted to shift a status bit indicating whether there is output data in an output buffer of the external system, the status bit being transmitted to the integrated circuit. 10. The integrated circuit according to claim 1, wherein the register is a shift register having at least one input operatively coupled to the external device, the shift register shifting at least one input a plurality of status bits to the integrated circuit over the at least one input. 11. The integrated circuit according to claim 10, wherein the plurality of status bits are located closest to a transmission end of a shift register associated with the external system. 12. The integrated circuit according to claim 1, wherein the external device is configured to poll the register at regular intervals. 13. The integrated circuit according to claim 1, wherein the data message is a variable length message. 14. An integrated circuit comprising:an interface for communicating information to an external device, the interface having an output buffer configured to store a plurality of data bits representing an output data message, the interface providing an indication to the external device that the data message is available to be transmitted to the external device;wherein the integrated circuit includes a shift register, wherein the shift register includes one or more status bits indicating that one or more valid data words of the data message are available to be transmitted to the external device. 15. The integrated circuit according to claim 14, wherein the external device is configured to poll only the one or more status bits to determine if the one or more data words are available to be transmitted. 16. The integrated circuit according to claim 15, wherein the external device is further configured to shift out data from the shift register, and is further configured to shift out only the one or more data words that are valid data words.