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Methods and devices for a memory system are disclosed. A digital memory device can receive power-down commands during the pendency of an active-mode command such as a burst read or write, that is, “early”. The device shuts down some circuitry, such as address and command registers, imm

Methods and devices for a memory system are disclosed. A digital memory device can receive power-down commands during the pendency of an active-mode command such as a burst read or write, that is, “early”. The device shuts down some circuitry, such as address and command registers, immediately upon receipt of the early power-down command. Other device components, e.g., those involved in servicing the burst read or write, remain active at least until their portion of the command has been completed. In some embodiments, the early power-down command can be issued concurrently with an active-mode command as an option to that command, freeing a memory controller from having to schedule and issue power-down commands separately. Significant power savings, as compared to those obtained with prior-art memory device power-down modes, are possible.

대표청구항 ▼

1. A memory system comprising:at least one multi-component memory device comprising power-down logic capable of accepting an early power-down command and responding to that early power-down command by shutting down some memory device components prior to the completion of a pending active-mode comman

1. A memory system comprising:at least one multi-component memory device comprising power-down logic capable of accepting an early power-down command and responding to that early power-down command by shutting down some memory device components prior to the completion of a pending active-mode command; anda memory controller to issue commands to the memory device, the controller capable of issuing the early power-down command to the memory device. 2. The memory system of claim 1, wherein an early power-down command can comprise an option issued by the memory controller concurrently with the issuance of an active-mode command. 3. The memory system of claim 1, wherein the early power-down command has at least two options, each option differing from the other in the number and/or timing of memory device components shut down in response to the power-down command. 4. The memory system of claim 1, wherein the memory device components, including the power-down logic, are integrated on a single integrated circuit. 5. A memory device comprising:a memory cell array;first circuitry to receive external address and command signals, and to control memory operations in response to received commands;second circuitry to interface the memory cell array with an external data bus; andpower-down logic capable of responding to an early power-down command by shutting down at least part of the first circuitry prior to the completion of a pending active-mode command and shutting down additional circuitry after completion of the pending active-mode command. 6. The memory device of claim 5, wherein the first circuitry comprises clocked address and command registers, and wherein the power-down logic comprises first disable logic to disable clock signals coupled to the address and command registers, in response to a power-down command, while an active-mode command is pending. 7. The memory device of claim 6, wherein the second circuitry comprises clocked memory cell array access logic and clocked external-data-bus registers, and wherein the power-down logic further comprises second disable logic to disable second clock signals coupled to the array access logic and external-data-bus registers, in response to an early power-down command, the second disable logic delaying the second clock signal disable until the completion of a pending active-mode command that uses the external-data-bus registers. 8. The memory device of claim 7, wherein the external-data-bus registers include receive registers operable in response to clock strobe signals received on an external data bus, the power down logic comprising third disable logic to disable clock strobe signal operation early when a pending active-mode command does not use the receive registers. 9. The memory device of claim 7, further comprising a delay-locked-loop circuit capable of synchronizing to an external clock signal, the memory device having at least one first power-down mode that does not power-down the delay-locked-loop circuit. 10. The memory device of claim 9, having at least one second power-down mode that executes a power-down of the delay-locked-loop circuit. 11. The memory device of claim 5, wherein the power-down logic shuts down the at least part of the first circuitry by selectively disabling clock signals to that circuitry. 12. The memory device of claim 5, capable of receiving a power-down command as a power-down option to an active-mode command. 13. The memory device of claim 12, wherein the first circuitry to receive external address and command signals comprises a command register and an address register of a given bit width, and wherein the active-mode commands comprise a write command and a read command, each issued to the command register along with an accompanying column address issued to the address register but not occupying the full address register width, the power-down option comprising the assertion of a signal, during the issuance of a read or write command, on at least one bit of the address register not used for the column address. 14. The memory device of claim 13, wherein the power-down option uses more than one bit of the address register not used for the column address, and wherein the assertion of different bit patterns as the power-down option indicates different power-down modes. 15. The memory device of claim 13, wherein at least one bit of the command register is registered by a clock that is not gated by the power-down logic, that bit, when asserted, causing the power-down logic to power-up any shut-down circuitry on the device. 16. A memory controller comprising:an address/command bus driver;a data bus transceiver; andpower-down command logic capable of causing the address/command bus driver to drive an early power-down command to a controlled memory unit, prior to the completion of a data bus transceiver operation with that controlled memory unit. 17. The memory controller of claim 16, wherein the early power-down command comprises a power-down option supplied as part of an active-mode command driven by the address/command bus driver. 18. A method of operating a memory device comprising:accepting an externally supplied early power-down command; andshutting down part of the memory device not necessary to complete a pending active-mode command while the power-down command is early. 19. The method of claim 18, further comprising shutting down another part of the memory device when the pending active-mode command is complete. 20. The method of claim 18, wherein accepting an early power-down command comprises accepting a power-down-upon-completion option as part of an externally supplied active-mode command. 21. The method of claim 18, wherein accepting an early power-down command comprises interpreting which of several possible power-down modes is requested in the early power-down command, and changing the timing and/or selection of which parts of the memory device to shut down based on the interpreted power-down mode. 22. The method of claim 18, further comprising basing a selection of what part of the memory device is not necessary to complete a pending active-mode command on the particular active-mode command that is pending.