IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0809441
(2001-03-15)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
7 인용 특허 :
8 |
초록
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A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an integrated circuit. The two memory registers are programmed to provide two different soft-start settings for two distinct charge pump turn-on condit
A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an integrated circuit. The two memory registers are programmed to provide two different soft-start settings for two distinct charge pump turn-on conditions, initial power-up and flash programming. Charge pump feedback logic is employed to detect the charge pump turn-on condition and activate the proper pre-programmed soft-start setting loaded in the memory registers.
대표청구항
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1. A programmable soft-start control for a charge pump configured to provide a voltage output, a charge-off signal output when the voltage output is below a target voltage, a programable clock input to provide PFM control of the charge and discharge phase, and charge-strength selector inputs which s
1. A programmable soft-start control for a charge pump configured to provide a voltage output, a charge-off signal output when the voltage output is below a target voltage, a programable clock input to provide PFM control of the charge and discharge phase, and charge-strength selector inputs which set a voltage ramp-up rate of the voltage output, said soft-start control comprising:a charging-series circuit coupled to the charge-off signal output and the charge-strength selector inputs of the charge pump, said charging-series circuit is configured to provide turn-on outputs to the charge-strength selector inputs; andat least one frequency selector circuit configured to provide a clock pulse output that is used by said charging-series circuit for a specific soft-start condition of the charge pump, said at least one frequency selector circuit is programmed to select a frequency of said clock pulse output. 2. The soft-start control of claim 1, further comprising a detection and selection circuit coupled between said charging-series circuit and said at least one frequency selector circuit, said detection and selection circuit is configured to detect said specific soft-start condition of the charge pump and select, for said specific soft-start condition, said clock pulse output of said at least one frequency selector circuit to clock said charging-series circuit when said detection and selection circuit and said charging-series circuit receive the charge-off signal output from the charge pump. 3. The soft-start control of claim 1, wherein said charging-series circuit comprises a counter configured to provide a repeatable step series of turn-on outputs to the charge-strength selector inputs of the charge pump. 4. The soft-start control of claim 3, wherein said charging-series circuit further comprises, for each of said turn-on outputs of said counter, a respective synchronous gate and a respective AND gate, wherein each of said turn-on outputs is coupled to said respective synchronous gate and each respective synchronous gate is coupled to said respective AND gate, wherein said charging-series circuit is configured to provide said each of said turn-on outputs to the charge pump when said respective AND gate receives the charge-off signal output from the charge pump and an output from said respective synchronous gate. 5. The soft-start control of claim 1, wherein said at least one frequency selector circuit comprises a programmable memory register configured to provide digital logic that selects said frequency of said clock pulse output. 6. The soft-start control of claim 5, wherein said at least one frequency selector circuit further comprises a divide-by-n counter/prescaler having data inputs coupled to said programmable memory register which set a frequency division of said divide-by-n counter/prescaler, said divide-by-n counter/prescaler is configured to provide said clock pulse output. 7. The soft-start control of claim 6, wherein said at least one frequency selector circuit further comprises a T flip-flop and a multiplexer coupled to clock inputs of both said divide-by-n counter/prescaler and said T flip-flop, said T flip-flop is configured to receive said clock pulse output of said divide-by-n counter/prescaler and is configured to output said clock pulse output on a clock pulse from said multiplexer. 8. The soft-start control of claim 2, wherein said at least one frequency selector circuit comprises two frequency selector circuits, each of said two frequency selector circuits is configured to provide said clock pulse output for a specific soft-start condition of the charge pump. 9. The soft-start control of claim 8, wherein said detection and selection circuit comprises a two-to-one multiplexer having its inputs coupled to said two frequency selector circuits, and a D flip-flop configured to receive the charge-off signal output of the charge pump and an external pump turn-on signal in order to correctly switch said two-to-one multiplexer to said clock pulse output of said frequency selection circuit for said specific soft-start condition. 10. A programmable soft-start control for a charge pump configured to provide a voltage output, a charge-off signal output when the voltage output is below a target voltage, and charge-strength selector inputs which set a voltage ramp-up rate of the voltage output, said soft-start control comprising:a charging-series circuit coupled to the charge-off signal output and the charge-strength selector inputs of the charge pump, wherein said charging-series circuit is configured to provide turn-on output to the charge-strength selector inputs of the charge pump;a pair of frequency selector circuits each configured to provide a respective clock pulse output that is used by said charging-series circuit for a specific operating condition of the charge pump, wherein each said pair of frequency selector circuits comprises a programmable memory register that is programmed to select a frequency of said respective clock pulse output; anda detection and selection circuit coupled between said charging-series circuit and said pair of frequency selector circuits, said detection and selection circuit is configured to detect said specific soft-start condition of the charge pump and select, for said specific soft-start condition, said respective clock pulse output of one of said pair of frequency selector circuits to clock said charging-series circuit when said detection and selection circuit and said charging-series circuit receive the charge-off signal output from the charge pump. 11. The soft-start control of claim 10, wherein said programmable memory of each said pair of frequency selector circuits comprises 8 bits of programmable memory. 12. The soft-start control of claim 10, wherein said turn-on outputs comprise a binary series. 13. The soft-start control of claim 12, wherein said charging-series circuit provides at least three outputs, each of said three outputs represents a respective significant bit in said binary series, each of said at least three outputs is coupled to one of the charge-strength selector inputs of the charge pump, and provides an input to the charge pump when said charging-series circuit receives the charge-off signal output from the charge pump and said respective significant bit in said binary series is active. 14. The soft-start control of claim 13, wherein said binary series consists of 001, 010, 100, 011, 101, 110, 111. 15. The soft-start control of claim 10, wherein each of said pair of frequency selector circuits further comprises a divide-by-n counter/prescaler having data inputs coupled to said programmable memory register which set a frequency division of said divide-by-n counter/prescaler, said divide-by-n counter/prescaler configure to provide said respective clock pulse output. 16. The soft-start control of claim 15, wherein each said pair of frequency selector circuits further comprises a T flip-flop and a multiplexer coupled to clock inputs of both said divide-by-n counter/prescaler and said T flip-flop, said T flip-flop is configured to receive said respective clock pulse output of said divide-by-n counter/prescaler and is configured to output said respective clock pulse output on a clock pulse from said multiplexer. 17. The soft-start control of claim 10, wherein said detection and selection circuit further comprises a two-to-one multiplexer having its inputs coupled to said pair of frequency selector circuits, and a D flip-flop configured to receive the charge-off signal output of the charge pump and an external pump turn-on signal in order to correctly switch said two-to-one multiplexer to said clock pulse output of said frequency selection circuit for said specific soft-start condition. 18. A method for controlling a voltage ramp-up rate of a charge pump configured to provide an output voltage under specific soft-start conditions, the charge pump having charge-strength selector inputs that set a voltage ramp-up rate of the output voltage, the method comprising:programming at least one memory register to set both a divisor for a divide-by-n counter/prescaler and a clock signal input for a specific soft-start condition of the charge pump;producing a clock signal pulse of a specific frequency based on digital logic stored in said at least one memory register;driving a charging-series output with said clock signal pulse at said specific frequency; andproviding said charging-series output to the charge-strength selector inputs of the charge pump to vary the voltage ramp-up rate of the output voltage of the charge pump for each of the specific soft-start condition. 19. The method of claim 18, wherein said at least one memory register comprises two memory registers and said method further comprises detecting said specific soft-start condition of the charge pump and providing said clock signal pulse produced according to said digital logic of one of said two memory registers for said detected specific soft-start condition to drive said charging-series output. 20. A programmable soft-start control for use with an external circuit, said control comprising:a pair of frequency selector circuits each having programmable memory, a multiplexer adapted to receive clock signal inputs from the external circuit and having selection inputs and a selected output, a counter having data inputs for setting a frequency of a clock pulse output, and a gate circuit, each of said data inputs of said counter and each of said selection inputs of said multiplexer are coupled to a separate bit register of said memory, said selected output of said multiplexer is coupled both to a clock input of said counter and a clock input of said gate;a charging-series circuit comprising a bit counter configured to provide a series of outputs; anda detection and selection circuit having a multiplexer and a flip-flop circuit, said multiplexer is coupled to said gate of each of said pair of frequency selector circuits such that said multiplexer provides said clock pulse output of said counter to clock said bit counter of said charging-series circuit, said flip-flop is configured to set which one of said pair of frequency selector circuits provides said clock pulse output to said charging-series circuit based on input from the external circuit. 21. An apparatus comprising:a flash memory;a charge pump configured to provide a voltage output to said flash memory, a charge-off signal output when said voltage output is below a target voltage for at least two specific operating conditions of the charge pump, a programmable clock input to provide PFM control of the charge and discharge phase, and charge-strength selector inputs which set a voltage ramp-up rate of said voltage output; anda soft-start control coupled to said charge-strength selector inputs of said charge pump and configured to provide a binary series output which causes said voltage output of said charge pump to reach said target voltage in a time period having a series of voltage ramp-up rate steps, said soft-start control comprising a counter configured to produce said binary series output, a programmable memory register for each of said at least two specific operating conditions of said charge pump, said programmable memory register is configured to select a frequency of said binary series output, and a detection and selection circuit adapted to detect said specific operating condition of the charge pump and select the correct said binary series output for said specific operating condition when said detection and selection circuit and said counter receive the charge-off signal output from the charge pump. 22. The apparatus of claim 21, wherein said apparatus comprises a flash memory card and said flash memory comprises a plurality of non-volatile, flash electrically erasable programmable read only memory (EEPROM) chips, a flash control circuit for controlling, erasing, writing, and reading operat ions of said flash memory, and a clock driver circuit for providing said clock input to said soft-start control. 23. The apparatus of claim 21, wherein said at least two specific operating conditions comprise charge pump initial turn-on and flash programming of said flash memory. 24. A host system comprising:a system bus for communicating information through said host system;a voltage supply for providing voltage over said system bus;a processor coupled to said system bus and configured to process instructions;main memory coupled to said processor and configured to temporarily store said instructions and data for said processor;read-only memory coupled to said system bus and configured to store static information for said processor;an input device coupled to said system bus and configured to accept said instruction and data;an output device coupled to said system bus; anda flash memory device coupled to said system bus, said flash memory device is comprised of a charge pump configured to provide a voltage output, a charge-off signal output when said voltage output is below a target voltage for at least two specific operating conditions of said charge pump, and charge-strength selector inputs configured to set a voltage ramp-up rate of said voltage output, and a programmable soft-start control coupled to said charge-strength selector inputs of said charge pump and configured to provide a binary series output to control a time period said voltage output of said charge pump reaches said target voltage with a series of voltage ramp-up rate steps. 25. The host system of claim 24, wherein said flash memory device further comprises at least one non-volatile, flash EEPROM chip, a flash control circuit for controlling erasing, writing, and reading operations of said flash memory chip, and a clock driver circuit for providing a circuit timing. 26. The host system of claim 24, wherein said soft-start control further comprises:a counter configured to produce said binary series output,a programmable memory register for each of said at least two specific operating conditions of said charge pump, wherein said programmable memory register selects a frequency of said binary series output, anda detection and selection circuit configured to detect said specific operating condition of the charge pump and select the correct said binary series output for said specific operating condition when said detection and selection circuit and said counter receive the charge-off signal output from the charge pump. 27. The host system of claim 24, wherein said flash memory device is removable. 28. A programmable soft-start control for a charge pump configured to provide a voltage output, a charge-off signal output when the voltage output is below a target voltage, and charge-strength selector inputs which set a voltage ramp-up rate of the voltage output, said soft-start control comprising:a charging-series circuit coupled to the charge-off signal output and the charge-strength selector inputs of the charge pump, wherein said charging-series circuit is configured to provide turn-on output to the charge-strength selector inputs of the charge pump;a pair of frequency selector circuits each configured to provide a respective clock pulse output that is used by said charging-series circuit for a specific operating condition of the charge pump, wherein each said pair of frequency selector circuits comprises:a programmable memory register configured to provide digital logic,a multiplexer configured to receive said digital logic and various clock frequency pulses, wherein said multiplexer is configured to output one of said various clock frequency pulses based on said digital logic,a divide-by-n counter/prescaler configured to receive said one of said various clock frequency pulses and said digital logic, said digital logic sets a frequency division of said divide-by-n counter/prescaler, wherein said divide-by-n counter/prescaler is configured to provide said clock pul se output as the frequency division of said received clock frequency pulse, anda T flip-flop configured to receive said one of said various clock frequency pulses and said clock pulse output, wherein said T flip-flop is configured to output said clock pulse output on a clock pulse of said one of said various clock frequency pulses; anda detection and selection circuit coupled between said charging-series circuit and said T flip-flop of each said frequency selector circuits, said detection and selection circuit is configured to detect said specific soft-start condition of the charge pump and select, for said specific soft-start condition, said clock pulse output from said T flip-flop of one of said pair of frequency selector circuits to clock said charging-series circuit when said detection and selection circuit and said charging-series circuit receive the charge-off signal output from the charge pump.
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