Method and circuit arrangement for implementing inter-system synchronization in a multimode device
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-007/00
H04J-003/06
출원번호
US-0504995
(2000-02-15)
우선권정보
FI-990361 (1999-02-19)
발명자
/ 주소
Ranta, Jukka
출원인 / 주소
Nokia Mobile Phones Ltd.
대리인 / 주소
Perman & Green LLP
인용정보
피인용 횟수 :
16인용 특허 :
4
초록▼
A method is presented for implementing synchronization between the timing of a first telecommunication system and the timing of a second telecommunication system. A first counter value is regularly updated at a pace determined by the first telecommunication system and a second counter value is regul
A method is presented for implementing synchronization between the timing of a first telecommunication system and the timing of a second telecommunication system. A first counter value is regularly updated at a pace determined by the first telecommunication system and a second counter value is regularly updated at a pace determined by the second telecommunication system. At a first time instant the current first counter value is stored. At a second, later time instant the stored counter value is read. Using the read counter value an operational step is timed so that its timing in relation to the timing of the first telecommunication system is known.
대표청구항▼
1. A method for implementing synchronization between the timing of a first telecommunication system and the timing of a second telecommunication system, comprising the steps of:a) regularly updating a first counter value at a pace determined by the first telecommunication system, the pace being rela
1. A method for implementing synchronization between the timing of a first telecommunication system and the timing of a second telecommunication system, comprising the steps of:a) regularly updating a first counter value at a pace determined by the first telecommunication system, the pace being related to a time base of the first telecommunication system,b) regularly updating a second counter value at a pace determined by the second telecommunication system, the pace being related to a time base of the second telecommunication system, the time base of the second telecommunication system being different than the time base of the first telecommunication system,c) at a first time instant reading the current first counter value and storing the read first counter value into a storage location different from the counter itself,d) at a second, later time instant reading the counter value stored at step c) ande) using the counter value read at step d) to time an operation performed by a processor so that the timing of the operation in relation to the timing of the first telecommunication system is known. 2. A method according to claim 1, comprising, as a part of step c), the step of storing the current first and second counter values. 3. A method according to claim 2, wherein the storing of the current first and second counter values takes place as a response to a common triggering signal. 4. A method according to claim 1, additionally comprising the steps ofc′) at a third time instant storing the current second counter value,d′) at a fourth, later time instant reading the counter value stored at step c′) ande′) using the counter value read at step d′) to time an operation performed by the processor so that the timing of the operation in relation to the timing of the second telecommunication system is known. 5. A method according to claim 4, wherein said third time instant is the same as said first time instant. 6. A method according to claim 1, additionally comprising the steps ofc″) at multiple time instants following said first time instant storing the current first counter value,d″) reading the counter values stored at step c″) ande″) at step e) using additionally the counter values read at step d″) to time an operation performed by the processor so that the timing of the operation in relation to the timing of the first telecommunication system is known. 7. A circuit arrangement for implementing synchronization between the timing of a first telecommunication system and the timing of a second telecommunication system, comprising:a first counter associated with a time base of the first telecommunication system and a second counter associated with a time base of the second telecommunication system, wherein the time base of the first telecommunication system is not common to the time base of the second telecommunication system,first snapshot storage means responsive to a first triggering signal for storing the value of said first counter that coincides with the reception of said first triggering signal, anda processor for reading the stored value of said first counter and for timing an operation performed by the processor so that the timing of the operation in relation to the timing of the first telecommunication system is known. 8. A circuit arrangement according to claim 7, additionally comprising second snapshot storage means responsive to a second triggering signal for storing the value of said second counter that coincides with the reception of said second triggering signal. 9. A circuit arrangement according to claim 8, wherein said second snapshot storage means is responsive to the same triggering signal as said first snapshot storage means. 10. A circuit arrangement according to claim 9, wherein said processor is arranged to issue the combined first and second triggering signal. 11. A circuit arrangement according to claim 8, comprising means for generating said first triggering signal as a response to a certain predetermined state of said second counter and means for generating said second triggering signal as a response to a certain predetermined state of said first counter. 12. A circuit arrangement according to claim 7, wherein said first snapshot storage means is arranged to store multiple values of said first counter. 13. A circuit arrangement according to claim 7, comprising, outside said processor, a triggering signal generator for generating said first triggering signal. 14. A radio telecommunication device for communicating with a first telecommunication system and a second telecommunication system, comprising a first radio transceiver and a second radio transceiver and within each radio transceiver for generating a frame time counter input clock, comprising:a first counter responsive to the frame time counter input clock generated in the first radio transceiver,a second counter responsive to the frame time counter input clock generated in the second radio transceiver, wherein the frame time counter input clock generated in the first radio transceiver is isolated from and not common to the frame time counter input clock generated in the second radio transceiver,first snapshot storage means responsive to a first triggering signal for storing the value of said first counter that coincides with the reception of said first triggering signal, anda processor for reading the stored value of said first counter and for timing an operation performed by the processor so that the timing of the operation in relation to the timing of the first telecommunication system is known. 15. A method of synchronizing a timing between a timing of a first telecommunication system and a timing of a second telecommunication system comprising:updating a first counter value at a pace determined by the first telecommunication system;updating a second counter value at a pace determined by the second telecommunication system wherein the pace determined by the first telecommunication system is not related to the pace determined by the second telecommunication system;at a first time instant in response to a common triggering signal, storing a current first and a current second counter value;at a subsequent time instant reading the stored current first and second counter values; andusing the read stored current first and second counter values to time an operation of a processor so that the timing of the operation in relation to the timing of the first telecommunication system is known. 16. The method of claim 15 further comprising:at a third time instant storing the current second counter value;at a fourth, later time instant reading the counter value stored at the third time instant; andusing the counter value read at the fourth, later time instant, to time an operation of the processor so that the timing of the operation in relation to the timing of the second telecommunication system is known. 17. The method of claim 16 wherein the third time instant is the same as the first time instant. 18. The method of claim 15 further comprising:at multiple time instants following the first time instant storing the current first counter value;reading the counter values stored at the multiple time instants; andusing the read stored current first and second counter values to time another operation of the processor, using additionally the counter values read at the multiple time instants to time the operation of the processor so that the timing of another operation in relation to the timing of the first telecommunication system is known. 19. The circuit arrangement of claim 7 wherein the first snapshot storage means responsive to the first triggering signal reads the value of the first counter that coincides with the reception of the first triggering signal and stores the read value in a storage location different from the counter itself. 20. The radio telecommunication device of claim 14 wherein the first snapshot storage means responsive to the first triggering signal reads the value of the first counter that coincides with the reception of the first triggering signal and stores the read value in a storage location different from the counter itself. 21. A method of arranging a timing in a single telecommunication device operating in at least two mutually separate telecommunication systems comprising:determining a timing of an operation in a first telecommunication system having a first time base by regularly updating a first counter value at a pace determined by the first telecommunication system, the pace being related to a time base of the first telecommunication system, and at a first time instant reading the current first counter value and storing the read first counter value into a storage location different from the counter itself;determining a timing of an operation in a second telecommunication system having a second time base mutually exclusive from the first time base by regularly updating a second counter value at a pace determined by the second telecommunication system, the pace being related to a time base of the second telecommunication system, the time base of the first telecommunication system being different than the time base of the second telecommunication system, at a second, later time instant reading the stored read first counter value; andthe second telecommunication system using the determined timing in the first telecommunication system to time an operation in the single telecommunication device by using the counter value read at the second, later time instant to time an operation performed by a processor so that the timing of the operation in relation to the timing of the first telecommunication system is known.
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이 특허에 인용된 특허 (4)
Farwell Charles Y. (Denver) Hearn Michel L. (Broomfield) Heidebrecht Richard M. (Boulder CO) Ho Kelvin K. (Somerset NJ) Spencer Douglas A. (Boulder CO), Adaptive synchronization arrangement.
Read E. Lawrence (Plano TX) Hanson Gary D. (Plano TX) Sensel Steven D. (The Colony TX) Schroder Richard (Plano TX), Integrated multi-fabric digital cross-connect timing architecture.
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