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Method and system for implementing a sigma delta analog-to-digital converter

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03M-001/12
  • H03M-003/00
출원번호 US-0321509 (2002-12-18)
발명자 / 주소
  • Erdogan, Alper Tunga
  • Lu, Chung-Li
  • Halder, Bijit
출원인 / 주소
  • GlobespanVirata, Inc.
대리인 / 주소
    Hunton & Williams LLP
인용정보 피인용 횟수 : 10  인용 특허 : 52

초록

An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comp

대표청구항

1. An analog-to-digital converter comprising:a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal; anda multistage decimator structure for receiving the combined signal and generating a digi

이 특허에 인용된 특허 (52)

  1. Choi Young-Bae,KRX, Add-compare-select processor in Viterbi decoder.
  2. Wilson James ; Cellini Ronald A. ; Sobol James M., Analog to digital conversion using nonuniform sample rates.
  3. Robert M. Schreiber ; Binan Wang, Analog-to-digital converter including two-wire interface circuit.
  4. Kaku Takashi (Kawasaki JPX) Okita Ryoji (Kawasaki JPX) Miyazawa Hideo (Kawasaki JPX), Automatic equalizer with a branched input for improved accuracy.
  5. Panasik, Carl M.; Viswanathan, T. R., Base station having high speed, high resolution, digital-to-analog converter with off-line sigma delta conversion and storage.
  6. Shahar Menashe,ILX ; Albo Claude,ILX ; Hendler Hillel,ILX, Data communication device for CATV networks.
  7. Choi Hyung-Jin,KRX ; Cho Sung-Bae,KRX ; Jung Suk-Jin,KRX ; Lee Hyung-Kil,KRX, Decoding method and apparatus using trace deletion for Viterbi algorithm.
  8. Jean-Luc De Gouy FR; Pascal Gabet FR; Philippe Benabes FR, Delay compensation for analog-to-digital converter in sigma-delta modulators.
  9. Minoru Takeda JP; Yoshihiro Hanada JP, Delta sigma digital-to-analog converter.
  10. Cake Brian ; Leslie Thomas Coutts,GBX, Delta sigma-analog-to-digital converter.
  11. Hanada Yoshihiro,JPX ; Toyama Akira,JPX, Delta-sigma D/A converter.
  12. Liu, Shen-Iuan; Kuo, Chien-Hung; Hsueh, Tzu-Chien; Chang, Hsiang-Hui, Delta-sigma modulator.
  13. Lin Kun (Austin TX), Digital decimation filter for delta sigma analog-to-digital conversion with reduced hardware compelexity.
  14. Gabriele Gandolfi IT; Andrea Baschirotto IT; Vittorio Colonna IT; Paolo Cusinato IT, Digital-analog converter comprising a third order sigma delta modulator.
  15. Takafumi Esaki JP, Digital/analog converter having delta-sigma type pulse modulation circuit.
  16. Chen Walter Y., Direct equalization method.
  17. Ho Edmond Y. (Colts Neck Township ; Monmouth County NJ), Equalizer sample loading in voiceband data sets.
  18. Otani Susumu (Tokyo JPX), Error correction apparatus using a Viterbi decoder.
  19. Abbey Duane L., High performance sigma-delta-sigma low-pass/band-pass modulator based analog-to-digital and digital-to-analog converter.
  20. Thayamkulangara R. Viswanathan, High speed, high resolution digital-to-analog converter with off-line sigma delta conversion and storage.
  21. Brown Glen W., Implementation of a digital decimation filter and method.
  22. William J. Martin, Integrated multi-mode bandpass sigma-delta receiver subsystem with interference mitigation and method of using same.
  23. Feng Wang ; Michael J. Gaboury, Mapping a delta-sigma converter range to a sensor range.
  24. Koizumi Fumiaki,JPX, Maximum-likelihood decoding.
  25. Auerbach Richard Allan ; Haymes Charles Louis ; Zumbo Dominick Anthony, Method and apparatus for creating virtual high bandwidth data channels.
  26. Zhong Yan ; Yang Lin ; Rafie Manouchehr, Method and apparatus for generating branch metrics and branch indices for convolutional code Viterbi decoders.
  27. Goodson Richard L. (Huntsville AL) Gusler ; Jr. Lee T. (Huntsville AL) Rushing Mickey C. (Harvest AL), Method and apparatus for initializing equalizer coefficents using peridioc training sequences.
  28. Mahibur Rahman ; Christopher T. Thomas, Method and architecture for complex datapath decimation and channel filtering.
  29. Chatter Mukesh, Method of and system architecture for high speed dual symmetric full duplex operation of asymmetric digital subscriber lines.
  30. Todoroki Toshiya (Tokyo JPX), Method of and system for data transmission employing trellis coded modulation.
  31. Timm William C. ; Chen Walter Y. ; Frantz Gene A. ; Garcia Domingo G. ; Lu Xiaolin ; Mannering Dennis G. ; Polley Michael O. ; Riley Terence J. ; Shaver Donald P. ; Wu Song ; Gatherer Alan ; Schurr P, Multimode digital modem.
  32. Hu Keren ; Lin William Wei-Lian ; Caldwell Maurice David, Multiple mode trellis decoder for a digital signal processing system.
  33. Vicard Dominique (Echirolles FRX) Glass William (Seyssinet-Pariset FRX) Druilhe Francois (Seyssins FRX), Process and a circuit for adapting coefficients in a modem equalizer.
  34. Lou Huiling (Stanford CA) Cioffi John M. (Cupertino CA), Programmable viterbi signal processor.
  35. Mittel James G., Sigma delta data converter with feed-forward path to stabilize integrator signal swing.
  36. Peter Laaser DE, Sigma-delta A/D converter.
  37. Pieter G. Blanken NL; Eric J. Van der Zwan NL; Eise C. Dijkmans NL, Sigma-delta analog-to-digital converter.
  38. Wada Masami,JPX, Sigma-delta analog-to-digital converter.
  39. Andreas Wiesbauer AT; Hubert Weinberger AT; Martin Clara AT; Jorg Hauptmann AT, Sigma-delta analog-to-digital converter array.
  40. Beomsup Kim KR; Taehoon Kim KR, Sigma-delta analog-to-digital converter using mixed-mode integrator.
  41. Roberto Sadkowski, Signal clipping circuit for switched capacitor sigma delta analog to digital converters.
  42. Victor Lee Hansen ; Charles L. Saxe, Sub-ranging analog-to-digital converter using a sigma delta converter.
  43. Choi Hyung-Jin,KRX ; Cho Sung-Bae,KRX ; Jung Suk-Jin,KRX ; Lee Hyung-Kil,KRX, Survivor memory device in viterbi decoder using trace deletion method.
  44. Chen, Feng, System and method for dynamic element matching.
  45. Li Chen ; Farhad Aminian ; Keith T. Chu, System and method of validating equalizer training.
  46. Gitlin Richard D. (Monmouth Beach NJ), Timing acquisition in voiceband data sets.
  47. Gitlin Richard D. (Monmouth Beach NJ) Ho Edmond Y. (Colts Neck Township ; Monmouth County NJ) Meadors ; Jr. Howard C. (Ocean NJ) Weinstein Stephen B. (Holmdel NJ), Timing acquisition in voiceband data sets.
  48. Ash Christopher P. (Caversham GB2), Transversal equalizers.
  49. Galpin Robert K. P. (Buckinghamshire GB2), Troposcatter modem receiver.
  50. Todoroki Toshiya (Tokyo JPX), Viterbi decoder for decoding error-correcting encoded information symbol string.
  51. Todoroki Toshiya (Tokyo JPX), Viterbi decoder for decoding error-correcting encoded information symbol string.
  52. Araki Satoru,JPX ; Shimazaki Yoshihito,JPX ; Ono Shigeru,JPX, Viterbi decoding method and circuit with accelerated back-tracing and efficient path metric calculation.

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  1. Roldan, Arianne B.; Im, Hsung Jai, Encoding scheme for processing pulse-amplitude modulated (PAM) signals.
  2. Wei, Changming; Chen, Yonggang, High accuracy temperature sensor.
  3. Wu, Song, HomePNA 10M8 compliant transceiver.
  4. May, Michael R.; Lowe, Erich, Integrated circuit having radio receiver and methods for use therewith.
  5. Runze, Gerhard; Burdenski, Ralf; Kalveram, Hans, Method and arrangement for setting the transmission of a mobile communication device.
  6. Ding,Lei; Melanson,John L.; Fei,Xaiofan; Gaboriau,Johann, Non-integer decimation using cascaded intergrator-comb filter.
  7. Lerdworatawee, Jongrit; Erden, Mehmet Fatih, Power efficient equalizer design.
  8. May,Michael R., Programmable sample rate analog to digital converter and method for use therewith.
  9. Veselinovic,Dusan S.; Radakovic,Daniela, System and method for efficient upsampled signal processing.
  10. Miller,Kevin Lee, System and method for shuffling mapping sequences.
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