초록 ▼

In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extendi

In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate. In another aspect, the invention features an integrated circuit package including a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, a semiconductor die electrically coupled with the conductive via, at least a portion of the semiconductor die being disposed inside the cavity of the substrate, an encapsulant material encapsulating a portion of the semiconductor die such that at least a portion of a surface of the semiconductor die is exposed.

대표청구항 ▼

1. A method of manufacturing an integrated circuit package, comprising:providing a substrate comprising:a first surface,a second surface opposite said first surface,a cavity through said substrate between said first and second surfaces, anda conductive via extending through said substrate and electr

1. A method of manufacturing an integrated circuit package, comprising:providing a substrate comprising:a first surface,a second surface opposite said first surface,a cavity through said substrate between said first and second surfaces, anda conductive via extending through said substrate and electrically connecting said first surface of said substrate with said second surface of said substrate;applying a strip to said second surface of said substrate;mounting a semiconductor die on said strip, at least a portion of said semiconductor die being disposed inside said cavity;encapsulating in a molding material at least a portion of said first surface of said substrate;removing said strip from said substrate; andattaching a thermal element to an exposed surface of said semiconductor die, wherein said attaching comprises attaching said thermal element to said conductive via. 2. The method of claim 1, said encapsulating further comprising filling said cavity with said molding material, wherein a surface of said semiconductor die is exposed to said strip. 3. The method of claim 1, said attaching said thermal element comprising bonding a thermally conductive adhesive to said thermal element. 4. The method of claim 3, said attaching said thermal element further comprising attaching said thermally conductive adhesive to said second surface of said substrate. 5. The method of claim 1, said mounting said semiconductor die comprising disposing said die in its entirety inside said cavity. 6. The method of claim 1, said thermal element comprising a heat slug. 7. The method of claim 1, said substrate further comprising a multi-layer circuit trace. 8. The method of claim 1, further comprising, after said mounting said semiconductor die on said strip, interconnecting said semiconductor die to a first trace embedded in said first surface of said substrate. 9. The method of claim 8, said interconnecting comprising a thermo-sonic wire bonding process. 10. The method of claim 1, said encapsulating comprising a liquid molding process. 11. The method of claim 1, said encapsulating comprising a transfer molding process. 12. The method of claim 1, said encapsulating comprising encapsulating said first surface of said substrate substantially in its entirety. 13. The method of claim 1, further comprising attaching a solder element to a trace embedded in said first surface of said substrate. 14. The method of claim 1, said applying said strip comprising applying an adhesive material on at least a portion of said strip to said second surface of said substrate. 15. The method of claim 1, said strip comprising a high temperature stable polyimide. 16. The method of claim 14, said mounting said semiconductor die comprising attaching said semiconductor die to said adhesive material on said strip. 17. The method of claim 1, said applying said strip further comprising sealing at least a portion of said cavity. 18. A method of manufacturing an integrated circuit package, comprising:providing a substrate comprising:a first surface,a second surface opposite said first surface,a plurality of cavities, each said cavity through said substrate between said first and second surfaces, anda plurality of conductive vias, each said via extending through said substrate and electrically connecting said first surface of said substrate with said second surface of said substrate;applying a strip to said second surface of said substrate;mounting a plurality of semiconductor dies on said strip, at least a portion of each said semiconductor die being disposed inside each said cavity;encapsulating in a molding material at least a portion of said first surface of said substrate;removing said strip from said substrate; andfor each of said plurality of semiconductor dies, attaching a thermal element to an exposed surface of each said semiconductor die, wherein said attaching comprises attaching said thermal element to at least one of said conductive vias. 19. The method of claim 18, fu rther comprising singulating said substrate into a plurality of integrated circuit packages. 20. The method of claim 19, said singulating comprising a sawing process. 21. The method of claim 19, said singulating comprising a punching process. 22. The method of claim 17, said applying said strip further comprising sealing an entire bottom portion of said cavity. 23. The method of claim 6, wherein said heat slug comprises copper. 24. The method of claim 1, wherein said integrated circuit package is a ball grid array integrated circuit package. 25. The method of claim 1, wherein said integrated circuit package is a land grid array integrated circuit package. 26. The method of claim 8, said interconnecting comprising a tape automated bonding process. 27. The method of claim 1, said substrate comprising a trace electrically connected to said conductive via. 28. The method of claim 27, said trace having a ring-like shape around said cavity. 29. The method of claim 1, said integrated circuit package having a thickness dimension of about 1.0 mm. 30. The method of claim 29, said integrated circuit package having a width dimension of about 7 to 50 mm. 31. The method of claim 30, said integrated circuit package having a width dimension of about 35 mm. 32. The method of claim 3, said thermally conductive adhesive comprising an epoxy. 33. The method of claim 32, said thermally conductive adhesive comprising a silver-filled epoxy. 34. A method of manufacturing an integrated circuit package, comprising:providing a substrate comprising:a first surface,a second surface opposite said first surface,a cavity through said substrate between said first and second surfaces, anda means for electrically connecting said first surface of said substrate with said second surface of said substrate;applying, to said second surface of said substrate, a means for sealing at least a portion of said cavity;mounting a semiconductor die on said means for sealing, at least a portion of said semiconductor die being disposed inside said cavity;encapsulating in a molding material at least a portion of said first surface of said substrate;removing said means for sealing from said substrate; andattaching, to at least an exposed surface of said semiconductor die, a means for dissipating heat, wherein said attaching comprises attaching said means for dissipating heat to said means for electrically connecting said first surface of said substrate with said second surface of said substrate. 35. The method of claim 34, said encapsulating further comprising filling said cavity with said molding material, wherein a surface of said semiconductor die is exposed to said means for sealing. 36. The method of claim 34, said attaching said means for dissipating heat comprising bonding a thermally conductive adhesive to said means for dissipating heat. 37. The method of claim 36, said attaching said means for dissipating heat further comprising attaching said thermally conductive adhesive to said second surface of said substrate. 38. The method of claim 34, said mounting said semiconductor die comprising disposing said die in its entirety inside said cavity. 39. The method of claim 34, said substrate further comprising a multi-layer circuit trace. 40. The method of claim 34, said encapsulating comprising encapsulating said first surface of said substrate substantially in its entirety. 41. The method of claim 34, said attaching a means for dissipating heat further comprising attaching said means for dissipating heat to said means for electrically connecting said first surface of said substrate with said second surface. 42. The method of claim 34, said integrated circuit package having a thickness dimension of about 1.0 mm. 43. The method of claim 42, said integrated circuit package having a width dimension of about 7 to 50 mm. 44. The method of claim 43, said integrated circuit package having a width dimension of about 35 mm. 45. The method of claim 18, said substrate comprising a trace electrically connected to said at least one conductive via. 46. The method of claim 45, said trace having a ring-like shape around said cavity. 47. The method of claim 34, said substrate comprising a trace electrically connected to said means for electrically connecting said first surface or said substrate with said second surface of said substrate. 48. The method of claim 47, said trace having a ring-like shape around said cavity.