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Power semiconductor devices having laterally extending base shielding regions that inhibit base reach-through 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
출원번호 US-0008171 (2001-10-19)
발명자 / 주소
  • Baliga, Bantval Jayant
출원인 / 주소
  • Silicon Semiconductor Corporation
대리인 / 주소
    Myers Bigel Sibley & Sajovec
인용정보 피인용 횟수 : 20  인용 특허 : 73

초록

A power MOSFET includes a semiconductor substrate having a drift region therein and a transition region that extends between the drift region and a first surface of the semiconductor substrate. The transition region has a vertically retrograded doping profile therein that peaks at a first depth rela

대표청구항

1. A vertical power device, comprising:a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of said semiconductor substrate, said transition region having a vert

이 특허에 인용된 특허 (73)

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  7. Lidow Alexander (Manhattan Beach CA) Herman Thomas (Redondo Beach CA), High power MOSFET with low on-resistance and high breakdown voltage.
  8. Lidow Alexander (Manhattan Beach CA) Herman Thomas (Redondo Beach CA), High power MOSFET with low on-resistance and high breakdown voltage.
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  43. Yoshizawa Tetsuo (Yokohama JPX) Terayama Yoshimi (Odawara JPX) Kondo Hiroshi (Yokohama JPX) Sakaki Takashi (Tokyo JPX) Haga Shunichi (Yokohama JPX) Ichida Yasuteru (Machida JPX) Konishi Masaki (Ebina, Method of producing electrical connection members.
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이 특허를 인용한 특허 (20)

  1. Hébert, François, Bottom-drain LDMOS power MOSFET structure having a top drain strap.
  2. Zhao, Jian Hui, Double-gated vertical junction field effect power transistor.
  3. Poveda, Patrick, Forming of the periphery of a schottky diode with MOS trenches.
  4. Wang, Peilin; de Frésart, Edouard D.; Qin, Ganming; Zhou, Hongwei, High voltage TMOS semiconductor device with low gate charge structure and method of making.
  5. Hébert, François, Method of forming bottom-drain LDMOS power MOSFET structure having a top drain strap.
  6. Bhalla, Anup; Hebert, Francois; Ng, Daniel S., Planar split-gate high-performance MOSFET structure and manufacturing method.
  7. Bhalla,Anup; Hebert,Francois; Ng,Daniel S., Planar split-gate high-performance MOSFET structure and manufacturing method.
  8. Shirai, Nobuyuki; Matsuura, Nobuyoshi; Nakazawa, Yoshito, Power supply circuit having a semiconductor device including a MOSFET and a Schottky junction.
  9. Miura, Naruhisa; Nakata, Shuhei; Ohtsuka, Kenichi; Watanabe, Shoyu; Watanabe, Hiroshi, Semiconductor device.
  10. Miura, Naruhisa; Nakata, Shuhei; Ohtsuka, Kenichi; Watanabe, Shoyu; Watanabe, Hiroshi, Semiconductor device.
  11. Shirai, Nobuyuki; Matsuura, Nobuyoshi; Nakazawa, Yoshito, Semiconductor device.
  12. Shirai, Nobuyuki; Matsuura, Nobuyoshi; Nakazawa, Yoshito, Semiconductor device for use in a power supply circuit and having a power MOSFET and Schottky barrier diode.
  13. Shirai, Nobuyuki; Matsuura, Nobuyoshi; Nakazawa, Yoshito, Semiconductor device including a MOSFET.
  14. Shirai, Nobuyuki; Matsuura, Nobuyoshi; Nakazawa, Yoshito, Semiconductor device including a MOSFET and Schottky junction.
  15. Shirai, Nobuyuki; Matsuura, Nobuyoshi; Nakazawa, Yoshito, Semiconductor device including a MOSFET and a Schottky junction.
  16. Zhang, Qingchun; Agarwal, Anant; Jonas, Charlotte, Transistor with A-face conductive channel and trench protecting well region.
  17. Zhang, Qingchun; Agarwal, Anant; Jonas, Charlotte, Transistor with A-face conductive channel and trench protecting well region.
  18. Zhang, Qingchun; Agarwal, Anant; Jonas, Charlotte, Transistor with A-face conductive channel and trench protecting well region.
  19. Jones,David P., Trench FET with reduced mesa width and source contact inside active trench.
  20. Peake,Steven T., Trench-gate semiconductor devices.
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