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A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system

A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

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1. A system comprising:an input for receiving compressed video data;an input for receiving data representing graphics;a video decoder for processing the compressed video data to generate a video for displaying;a display engine for processing the data representing graphics to generate graphics for di

1. A system comprising:an input for receiving compressed video data;an input for receiving data representing graphics;a video decoder for processing the compressed video data to generate a video for displaying;a display engine for processing the data representing graphics to generate graphics for displaying; andmeans for overlaying the video and the graphics to generate an output video,wherein the display engine includes a plurality of line buffers that are used during conversion of a graphics format from a first format to a second format which is compatible with a video format, wherein the line buffers are implemented in a single-port RAM configured to simulate a dual-port RAM,wherein the single-port RAM has been configured to be twice as wide and half as deep, and wherein two words are concurrently read in a read operation during a first memory access cycle, and two words are concurrently written in a write operation during a second memory access cycle, andwherein the read operation during the first memory access cycle and the write operation during the second memory access cycle immediately following the first memory access cycle can be performed on a same one of the line buffers or different ones of the line buffers. 2. The system of claim 1 wherein the single-port RAM is comprised of a single-port SRAM. 3. The system of claim 1 wherein the input for receiving compressed video data, the input for receiving data representing graphics, the video decoder, the display engine and the means for overlaying the video and the graphics are integrated on an integrated circuit chip. 4. The system of claim 1 further comprising one or more local registers coupled to the single-port RAM, and the one or more local registers hold at least two words to be used during the write operation. 5. The system of claim 1 wherein the write operation waits until a next memory access cycle when both the read operation and the write operation are asked to be performed in a current memory access cycle. 6. The system of claim 1 wherein the display engine further includes a graphics filter for converting format from the first format to the second format. 7. The system of claim 6 wherein the graphics filter is used to convert the graphics format from an HDTV-compatible format to an SDTV-compatible format. 8. The system of claim 6 wherein the graphics filter is used to convert the graphics format from a first HDTV-compatible format to a second HDTV-compatible format. 9. The system of claim 8 wherein the first HDTV format is compatible with an HDTV 720p format, and the second HDTV format is compatible with an HDTV 1080i format. 10. The system of claim 1 wherein the compressed video data include MPEG-2 video data included in one or more MPEG-2 Transport streams. 11. The system of claim 1 wherein the video decoder is an MPEG-2 video decoder. 12. The system of claim 1 wherein the video for displaying includes an HDTV video. 13. The system of claim 1 wherein the video for displaying includes an SDTV video. 14. A method of processing video and graphics comprising the steps of:receiving compressed video data;receiving data representing graphics;processing the compressed video data to generate a video for displaying;processing the data representing graphics to generate graphics for displaying;overlaying the video and the graphics to generate an output video;converting a graphics format to a format compatible with a video format using a plurality of line buffers that are implemented on a single-port RAM configured to simulate a dual-port RAM,wherein converting the graphics format comprises concurrently reading two words in a read operation during a first memory access cycle and concurrently writing two words in a write operation during a second memory access cycle, andwherein the read operation during the first memory access cycle and the write operation during the second memory access cycle immediately following the first memory access cycle can be performed on a s ame one of the line buffers or different ones of the line buffers. 15. The method of claim 14 wherein the step of converting the graphics format further comprises the step of holding at least two words in one or more local registers coupled to the single-port RAM, to be used during the write operation. 16. The method of claim 14 wherein the step of converting the graphics format further comprises the step of postponing the write operation until a next memory access cycle when both the read operation and the write operation are asked to be performed in a current memory access cycle. 17. The method of claim 14 wherein the step of converting the graphics format comprises the step of converting the graphics format from an HDTV-compatible format to an SDTV-compatible format. 18. The method of claim 14 wherein the step of converting the graphics format comprises the step of converting the graphics format from a first HDTV-compatible format to a second HDTV-compatible format. 19. The method of claim 18 wherein the step of converting the graphics format from a first HDTV-compatible format to a second HDTV-compatible format comprises the step of converting the graphics format from an HDTV 720p format to an HDTV 1080i format. 20. The method of claim 18 wherein the step of receiving compressed video data comprises the step of receiving one or more MPEG-2 Transport streams including MPEG-2 video data. 21. The method of claim 20 wherein the step of processing the compressed video data comprises the step of decoding the MPEG-2 video data. 22. A memory access system comprising:an input for receiving first data;an output for providing second data;a plurality of line buffers implemented on a single-port RAM configured to simulate a dual-port RAM; andone or more registers to store at least two words of the first data to be used during a write operation,wherein two words of the second data are read concurrently from the line buffers in a read operation during a first memory access cycle, and two words of the first data are written concurrently to the line buffers in the write operation during a second memory access cycle, andwherein the read operation during the first memory access cycle and the write operation during the second memory access cycle immediately following the first memory access cycle can be performed on a same one of the line buffers or different ones of the line buffers. 23. The memory access system of claim 22 wherein the first data written into the line buffers are provided as the second data read from the line buffers. 24. The memory access system of claim 22 wherein the read operation has higher priority over the write operation. 25. The memory access system of claim 22 wherein the read operation is performed on even addresses. 26. The memory access system of claim 22 wherein the input and the output, respectively, include an input port and an output port, and wherein the input port and the output port are periodically reset.