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A method of designing a VLSI chip and a chip designed according to the method are described. The method includes the steps of early consideration of resistive and capacitive values during a VLSI chip design process. The method provides for estimation of signal routes between nodes of functional bloc

A method of designing a VLSI chip and a chip designed according to the method are described. The method includes the steps of early consideration of resistive and capacitive values during a VLSI chip design process. The method provides for estimation of signal routes between nodes of functional blocks to be incorporated in the chips. The estimation may be based on a floor plan describing the positioning of the functional blocks, a connectivity description identifying connections between ports of the blocks and physical and mechanical configuration parameters. The functional blocks and design of the layout may be hierarchical in nature. The signal route estimation may be based on control factors such as the specification of signal route establishment algorithms. The next step is to foliate the nodes followed by determining resistance and capacitance values corresponding to all or parts of the estimated signal routes. The resistive and capacitive values may be incorporated into a model and a connectivity net list may be generated.

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1. A method for VLSI chip design comprising the steps of: estimating signal routes between functional blocks; foliating nodes in the estimated signal routes; determining resistance and capacitance values for route segments between the foliated nodes of the estimated signal routes; and building a

1. A method for VLSI chip design comprising the steps of: estimating signal routes between functional blocks; foliating nodes in the estimated signal routes; determining resistance and capacitance values for route segments between the foliated nodes of the estimated signal routes; and building a model of said signal routes including resistance and capacitance values; wherein the VLSI chip design is in register transfer language. 2. A method according to claim 1 further comprising the step of: foliating nodes in estimated signal routes. 3. A method according to claim 1 further comprising the step of: generating a connectivity net list from said model. 4. A method according to claim 1 wherein said step of estimating is performed based on input of a floor plan and a connectivity description. 5. A method according to claim 4 wherein said step of estimating is performed in response to one or more control factor inputs. 6. A method according to claim 5 wherein said control factor input specifies a signal routing algorithm. 7. A method according to claim 4 wherein said step of estimating is performed based on input of signal route configuration parameters. 8. A method according to claim 7 wherein said signal route configuration parameters specify one or more of signal route material, physical size of signal route material or spacing. 9. A method according to claim 7 wherein said step of estimating is performed in response to one or more control factor inputs. 10. A method according to claim 9 wherein said control factor input specifies a signal routing algorithm. 11. A VLSI chip whose design was performed according to a method comprising the steps of: estimating signal routes between functional blocks; foliating nodes in the estimated signal routes; determining resistance and capacitance values for route segments between the foliated nodes of the estimated signal routes; and building a model of said signal routes including resistance and capacitance values; wherein the design is in register transfer language. 12. A VLSI chip according to claim 11 whose design was performed according to the method further comprising the step of: foliating nodes in estimated signal routes. 13. A VLSI chip according to claim 11 whose design was performed according to the method further comprising the step of: generating a connectivity net list from said model. 14. A VLSI chip according to claim 11 whose design was performed according to the method wherein said step of estimating is performed based on input of a floor plan and a connectivity description. 15. A VLSI chip according to claim 14 whose design was performed according to the method wherein said step of estimating is performed in response to one or more control factor inputs. 16. A VLSI chip according to claim 15 whose design was performed according to the method wherein said control factor input specifies a signal routing algorithm. 17. A VLSI chip according to claim 14 whose design was performed according to the method wherein said step of estimating is performed based on input of signal route configuration parameters. 18. A VLSI chip according to claim 17 whose design was performed according to the method wherein said signal route configuration parameters specify one or more of signal route material, physical size of signal route material or spacing. 19. A VLSI chip according to claim 17 whose design was performed according to the method wherein said step of estimating is performed in response to one or more control factor inputs. 20. A VLSI chip according to claim 19 whose design was performed according to the method wherein said control factor input specifies a signal routing algorithm. 21. A system for forming a VLSI chip design comprising: means for estimating signal routes between functional blocks; means for foliating nodes in the estimated signal routes; means for determining resistance and capacitance values for route segments between the foliated nodes of the estimat ed signal routes; and means for building a model of said signal routes including resistance and capacitance values; wherein the VLSI chip design is in register transfer language. 22. A method according to claim 1 wherein the estimating signal routes between functional blocks occurs prior to a layout for the VLSI chip design. 23. A VLSI chip according to claim 11 wherein the estimating signal routes between functional blocks occurs prior to a layout for the VLSI chip. 24. A system according to claim 21 wherein the estimating signal routes between functional blocks occurs prior to a layout for the VLSI chip design. 25. The method of claim 1 wherein determining comprises: determining resistance values and capacitance values for the estimated signal routes. 26. The method of claim 11 wherein determining comprises: determining resistance values and capacitance values for the estimated signal routes. 27. The system of claim 21 wherein the means for determining comprises: means for determining resistance values and capacitance values for the estimated signal routes.