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Wiring line and manufacture process thereof and semiconductor device and manufacturing process thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0356976 (2003-02-03)
우선권정보 JP-0376007 (1998-12-18); JP-0376008 (1998-12-18); JP-0372753 (1998-12-28)
발명자 / 주소
  • Ohtani, Hisashi
  • Yamazaki, Shunpei
출원인 / 주소
  • Semiconductor Energy Laboratory Co., Ltd.
대리인 / 주소
    Cook, Alex, McFarron, Manzo, Cummings & Mehler, Ltd.
인용정보 피인용 횟수 : 26  인용 특허 : 28

초록

To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal,

대표청구항

1. A method of manufacturing a semiconductor device comprising:forming a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer;patterning the multi-layered film to form a first wiri

이 특허에 인용된 특허 (28)

  1. Matsumoto Hiroshi (Hachioji JPX), Active matrix liquid crystal display having a peripheral driving circuit element.
  2. Yamazaki Shunpei,JPX ; Takemura Yasuhiko,JPX, Electro-optical device having silicon nitride interlayer insulating film.
  3. Friend Richard H. (Cambridge NY GBX) Burroughes Jeremy H. (New York NY) Bradley Donal D. (Cambridge GBX), Electroluminescent devices.
  4. Bothra Subhas ; Qian Ling Q., Integrated circuit structure having an air dielectric and dielectric support pillars.
  5. Konuma Toshimitsu (Kanagawa JPX) Nishi Takeshi (Kanagawa JPX) Shimizu Michio (Chiba JPX) Mori Harumi (Kanagawa JPX) Moriya Kouji (Kanagwa JPX) Murakami Satoshi (Kanagawa JPX), Liquid-crystal electro-optical apparatus and method of manufacturing the same.
  6. Hwang Jeong-Mo (Plano TX), Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain.
  7. Buynoski Matthew S., Low dielectric semiconductor device with rigid, conductively lined interconnection system.
  8. Bohr Mark T. ; Greason Jeffrey K., Memory cell design with vertically stacked crossovers.
  9. Dawson Robert, Metal layer interconnects with improved performance characteristics.
  10. Byun Jeong Soo,KRX ; Lee Byung Hak,KRX, Method for fabricating semiconductor device.
  11. Pollack Gordon P. (Richardson TX), Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate.
  12. Ohtani Hisashi (Kanagawa JPX) Miyanaga Akiharu (Kanagawa JPX) Fukunaga Takeshi (Kanagawa JPX) Zhang Hongyong (Kanagawa JPX), Method for manufacturing a semiconductor device.
  13. Ohtani Hisashi,JPX ; Miyanaga Akiharu,JPX ; Fukunaga Takeshi,JPX ; Zhang Hongyong,JPX, Method for manufacturing a semiconductor device.
  14. Beck Walter,DEX ; Roethlingshoefer Walter,DEX ; Nitsche Detlef,DEX, Method for manufacturing ceramic multilayer circuit.
  15. Kameyama Shuichi (Yokohama JPX) Kanzaki Koichi (Kawasaki JPX) Sasaki Yoshitaka (Yokohama JPX), Method for manufacturing semiconductor device utilizing selective etching and diffusion.
  16. Zhang Hongyong (Kanagawa JPX) Yamaguchi Naoaki (Kanagawa JPX) Takemura Yasuhiko (Kanagawa JPX), Method of manufacturing a semiconductor device.
  17. Friend Richard H. (Cambridge NY GBX) Burroughes Jeremy H. (New York NY) Bradley Donal D. (Cambridge GBX), Method of manufacturing of electrolumineschent devices.
  18. Park In-sun,KRX ; Kim Byung-hee,KRX ; Oh Se-jun,KRX ; Lee Sang-min,KRX, Methods of forming integrated circuit memory devices having improved electrical interconnects therein.
  19. Noguchi Ko,JPX, Semiconductor device and method of manufacturing the same in which degradation due to plasma can be prevented.
  20. Mametani Tomoharu,JPX ; Nagai Yukihiro,JPX, Semiconductor device with improved interconnection.
  21. Okumura Koichiro (Tokyo JPX), Semiconductor integrated circuits with specific pitch multilevel interconnections.
  22. Hu Yongjun ; Pan Pai-Hung ; Ping Er-Xuan ; Thakur Randhir P.S. ; DeBoer Scott, Semiconductor structure having a doped conductive layer.
  23. Hwang Jeong-Mo (Plano TX), Silicon on insulator device comprising improved substrate doping.
  24. Inoue Shunsuke (Yokohama JPX) Koizumi Toru (Yokohama JPX) Miyawaki Mamoru (Tokyo JPX) Sugawa Shigetoshi (Atsugi JPX), Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness.
  25. Lu Chang-Ming,TWX ; Lu Shu-Ying,TWX, Structure of a bonding pad for semiconductor devices.
  26. Kawasaki Ritsuko,JPX ; Kitakado Hidehito,JPX ; Kasahara Kenji,JPX ; Yamazaki Shunpei,JPX, Thin film transistors having ldd regions.
  27. Gardner Mark I. ; Wristers Derick J. ; Cheek Jon D., Transistor with integrated poly/metal gate electrode.
  28. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (26)

  1. Chen, Chien-Hua; Chen, Zhizhang; Meyer, Neal W., 3D interconnect with protruding contacts.
  2. Sun, Wein-Town; Li, Chun-Sheng; Yu, Jian-Shen, Dual gate layout for thin film transistor.
  3. Tanaka,Koichiro, Laser irradiation apparatus and method for manufacturing semiconductor device.
  4. Hioki, Tsuyoshi; Nakai, Yutaka; Fukushima, Noburu, Light emitting apparatus.
  5. Tateishi, Yoshinori; Ofuji, Masato; Kumomi, Hideya; Hayashi, Ryo, Light emitting display apparatus.
  6. Yamagata,Hirokazu, Light-emitting device and method of fabricating the same.
  7. Son, Dong-Jin, Manufacturing method of metal wire and thin transistor array panel.
  8. Yun, Su Yeon; Son, Dong Jin, Manufacturing method of metal wire and thin transistor array panel, and organic light emitting diode display.
  9. Lee, Je Hun; Bae, Yang Ho; Cho, Beom Seok; Jeong, Chang Oh, Method of fabricating a thin film transistor array panel.
  10. Sasagawa,Shinya; Yokoshima,Takashi; Monoe,Shigeharu, Method of manufacturing a semiconductor device.
  11. Takakusaki,Sadamichi; Igarashi,Yusuke; Nezu,Motoichi; Kusabe,Takaya, Method of manufacturing circuit device.
  12. Yamazaki, Shunpei; Suzawa, Hideomi; Ono, Koji; Kusuyama, Yoshihiro, Semiconductor device and fabrication method thereof.
  13. Yamazaki, Shunpei; Suzawa, Hideomi; Ono, Koji; Kusuyama, Yoshihiro, Semiconductor device and fabrication method thereof.
  14. Yamazaki, Shunpei; Suzawa, Hideomi; Ono, Koji; Kusuyama, Yoshihiro, Semiconductor device and fabrication method thereof.
  15. Yamazaki, Shunpei; Suzawa, Hideomi; Ono, Koji; Kusuyama, Yoshihiro, Semiconductor device and fabrication method thereof.
  16. Yamazaki, Shunpei; Suzawa, Hideomi; Ono, Koji; Kusuyama, Yoshihiro, Semiconductor device and fabrication method thereof.
  17. Yamazaki,Shunpei; Suzawa,Hideomi; Ono,Koji; Kusuyama,Yoshihiro, Semiconductor device and fabrication method thereof.
  18. Yamazaki,Shunpei; Suzawa,Hideomi; Ono,Koji; Kusuyama,Yoshihiro, Semiconductor device and fabrication method thereof.
  19. Kitakado, Hidehito; Kawasaki, Ritsuko; Kasahara, Kenji, Semiconductor device and manufacturing method thereof.
  20. Kitakado, Hidehito; Kawasaki, Ritsuko; Kasahara, Kenji, Semiconductor device and manufacturing method thereof.
  21. Kitakado, Hidehito; Kawasaki, Ritsuko; Kasahara, Kenji, Semiconductor device and manufacturing method thereof.
  22. Yamazaki, Shunpei; Suzawa, Hideomi; Kusuyama, Yoshihiro; Ono, Koji; Koyama, Jun, Semiconductor device and manufacturing method thereof.
  23. Yamazaki, Shunpei; Suzawa, Hideomi; Kusuyama, Yoshihiro; Ono, Koji; Koyama, Jun, Semiconductor device and manufacturing method thereof.
  24. Yamazaki, Shunpei; Suzawa, Hideomi; Kusuyama, Yoshihiro; Ono, Koji; Koyama, Jun, Semiconductor device and manufacturing method thereof.
  25. Yamazaki, Shunpei; Koyama, Jun; Takahashi, Masahiro; Kishida, Hideyuki; Miyanaga, Akiharu; Sugao, Junpei; Uochi, Hideki; Nakamura, Yasuo, Semiconductor device and method for manufacturing the same.
  26. Chinthakindi,Anil K.; Eshun,Ebenezer E., Thin film resistor with current density enhancing layer (CDEL).
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