Multimedia interface having a processor and reconfigurable logic
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/00
G06F-015/00
G06F-015/76
출원번호
US-0929515
(2001-08-14)
발명자
/ 주소
Muthujumaraswathy, Kumaraguru
Rostoker, Michael D.
출원인 / 주소
Kawasaki Microelectronics, Inc.
대리인 / 주소
Linden Gerald E.
인용정보
피인용 횟수 :
51인용 특허 :
47
초록▼
An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or digital, can be incorporated. The IC can als
An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or digital, can be incorporated. The IC can also contain audio/video CODECs to suit different standards, as well as other peripheral devices which may be required for multimedia applications. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
대표청구항▼
1. Multimedia interface, comprising:an intergrated circuit (IC) chip;a block of reconfigurable logic incorporated on the IC chip; anda block of media processor with a virtual instruction set capable of implementing a variety of multimedia algorithms incorporated on the IC chip separately from the re
1. Multimedia interface, comprising:an intergrated circuit (IC) chip;a block of reconfigurable logic incorporated on the IC chip; anda block of media processor with a virtual instruction set capable of implementing a variety of multimedia algorithms incorporated on the IC chip separately from the reconfigurable logic block;wherein the block of reconfigurable logic contains a least common denomination set of instruction for operating the block of media processor. 2. The multimedia interface, according to claim 1, further comprising audio and/or video CODEC incorporated on the IC chip. 3. The multimedia interface, according to claim 1, further comprising a phase locked loop (PLL) circuitry incorporated on the IC chip. 4. The multimedia interface according to claim 1, further comprising a programmable, fast serial interface core to interface to a serial interface standard incorporated on the IC chip. 5. The multimedia interface according to claim 1, further comprising a programmable CPU interface core incorporated on the IC chip. 6. The multimedia interface according to claim 1, further comprising a programmable memory interface (PMI) core incorporated on the IC chip. 7. The multimedia interface according to claim 1, further comprising a configuration port that allows a user access to the block of reconfigurable logic from off-chip. 8. Multimedia interface, comprising:an integrated circuit (IC) chip;a block of reconfigurable logic incorporated on the IC chip;a media processor block incorporated on the IC chip; andat least one additional core selected from the group consisting ofaudio and/or video CODECs for interfacing to external analog signals;phase locked loop (PLL) circuitry to reduce skew within various blocks within the IC chip;a programmable, fast serial interface core;a programmable CPU interface core;a programmable memory interface (PMI) core; andfurther comprising power-down circuitry, in combination with one or more of these additional cores, incorporated on the IC chip to provide power and/or processing savings when a given one of the cores is not in use. (no change) 9. Multimedia interface according to claim 8, wherein:the at least one additional core includes the audio and/or video CODEC; andthe power-down circuitry provides the power and/or processing savings when the audio and/or video CODEC is not in use. 10. Multimedia interface according to claim 8, wherein:the at least one additional core includes the PLL circuitry; andthe power-down circuitry provides the power and/or processing savings when the PLL circuitry is not in use. 11. Multimedia interface according to claim 8, wherein:the at least one additional core includes the serial interface core; andthe power-down circuitry provides the power and/or processing savings when the serial interface core is not in use. 12. Multimedia interface according to claim 11, wherein:the serial interface core is incorporated within the reconfigurable logic block. 13. Multimedia interface according to claim 8, wherein:the at least one additional core includes the programmable CPU interface core; andthe power-down circuitry provides the power and/or processing savings when the programmable CPU interface core is not in use. 14. Multimedia interface according to claim 13, wherein;the programmable CPU interface core is incorporated within the reconfigurable logic block. 15. Mutimedia interface according to claim 8, wherein:the at least one additional core includes the PMI core; andthe power-down circuitry provides the power and/or processing savings when the PMI core is not in use. 16. Multimedia interface according to claim 15, wherein:the programmable memory interface core is incorporated within the reconfigurable logic block. 17. The multimedia interface according to claim 8, wherein the media processor has a virtual instruction set capable of implementing a variety of multimedia algorithms. 18. Signal processing interface, comprising:an integrated circuit (IC) chip;a block of reconfigurable logic incorporated on the IC chip;a RISC core incorporated on the IC chip; andat least one additional core selected from the group consisting ofaudio and/or video CODEC for interfacing to external analog signals;phase locked loop (PLL) circuitry to reduce skew within various block within the IC chip;a programmable, fast serial interface core;a programmable CPU interface core;a programmable memory interface (PMI) core; andfurther comprising power-down circuitry, in combination with one or more of these additional cores, incorporated on the IC chip to provide power and/or processing saving when a given one of the cores is not in use. 19. Signal processing interface according to claim 18, wherein:the at least one additional core includes audio and/or video CODEC; andthe power-down circuitry provides the power and/or processing saving when the audio and/or video CODEC is not in use. 20. Signal processing interface according to claim 18, wherein:the at least one additional core includes the PLL circuitry; andthe power-down circuitry provides the power and/or processing savings when the PLL circuitry is not in use. 21. Signal processing interface according to claim 18, wherein:the at least one additional core includes the serial interface core; andthe power-down circuitry provides the power and/or processing saving when the serial interface core is not in use. 22. Signal processing interface according to claim 21, wherein:the serial interface core is incorporated within the reconfigurable logic block. 23. Signal processing interface according to claim 18, wherein:the at least one additional core includes the programmable CPU interface core; andthe power-down circuitry provides the power and/or processing saving when the programmable CPU interface core is not in use. 24. Signal processing interface according to claim 23, wherein:the programmable CPU interface core is incorporated within the reconfigurable logic block. 25. Signal processing interface according to claim 18, wherein:the at least one additional core includes the PMI core; andthe power-down circuitry provides the power and/or processing savings when the PMI core is not in use. 26. Signal processing interface according to claim 25, wherein:the programmable memory interface core is incorporated within the reconfigurable logic block. 27. Multimedia interface, comprising:an integrated circuit (IC) chip;a block of reconfigurable logic incorporated on the IC chip;a media processor block incorporated on the IC chip; anda programmable memory interface (PMI) core incorporated on the IC chip, the PMI core communicates with off-chip memory and configures it virtually into what is optimal for an application that demands non-standard size memory. 28. Signal processing interface, comprising:an integrated circuit (IC) chip;a block of reconfigurable logic incorporated on the IC chip;a RISC core incorporated on the IC chip; anda programmable memory interface (PMI) core incorporated on the IC chip, the PMI core communicates with off-chip memory and configures it virtually into what is optimal for an application that demands non-standard size memory.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (47)
Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Grice Donald G. (Kingston NY) Kogge Peter M. (Endicott NY) Kuchinski Dav, Advanced parallel array processor(APAP).
Dapp Michael C. (Endwell NY) Barker Thomas N. (Vestal NY) Dieffenderfer James W. (Owego NY) Knowles Billy J. (Kingston NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Rolfe David , Advanced parallel processor including advanced support hardware.
Kucukcakar Kayhan ; Chen Chih-Tung, Customizable instruction set processor with non-configurable/configurable decoding units and non-configurable/configurable execution units.
Razdan Rahul (Princeton MA) Grundmann Bill (Westboro MA) Smith Michael D. (Belmont MA), Dynamically programmable reduced instruction set computer with programmable processor loading on program number field an.
Britton Barry K. ; Cunningham Alan ; Leung Wai-Bor ; Stuby ; Jr. Richard G. ; Thompson James A., Field programmable gate array having a dedicated processor interface.
Guttag Karl M. (Houston TX) McDonough Kevin C. (Houston TX) Maggi Sergio (Houston TX), Graphics display processor, a graphics display system and a method of processing graphics data with control signals conn.
Read Christopher J. (Houston TX) Guttag Karl M. (Missouri City TX), Huffman decoding method, circuit and system employing conditional subtraction for conversion of negative numbers.
Read Christopher J. (Houston TX) Guttag Karl M. (Missouri City TX), Huffman encoding method, circuit and system employing most significant bit change for size detection.
Andrews William B. ; Britton Barry K. ; Hickey Thomas J. ; Modo Ronald T. ; Nguyen Ho T. ; Schadt Lorraine L. ; Singh Satwant, Hybrid programmable gate arrays.
Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Van Aken Jerry R. (Sugar Land TX) Guttag Karl M. (Missouri City TX) Poland Sydney W. (Katy TX), Iterative division apparatus, system and method employing left most one\s detection and left most one\s detection with e.
Guttag Karl M. (Missouri City TX) Poland Sydney W. (Katy TX) Balmer Keith (Bedford GB2), Memory store from a selected one of a register pair conditional upon the state of a selected status bit.
Wang Jerry Borjeng ; Harper Robert Vernon ; Shi Chih-Chung, Network controller which enables the local processor to have greater access to at least one memory device than the host.
Balmer Keith (Bedford GB2) Read Christopher J. (Houston TX), Packed word pair multiply operation forming output including most significant bits of product and other bits of one inpu.
Albu Lucian R. ; Britton Barry K. ; Leung Wai-Bor ; Stuby ; Jr. Richard G. ; Thompson James A. ; Zilic Zeljko, Programmable clock manager for a programmable logic device that can generate at least two different output clocks.
Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Retter E, SIMD/MIMD processing memory element (PME).
Guttag Karl M. (Missouri City TX) Balmer Keith (Bedford GB2) Gove Robert J. (Plano TX) Read Christopher J. (Houston TX) Golston Jeremiah E. (Sugar Land TX) Poland Sydney W. (Katy TX) Ing-Simmons Nich, Three input arithmetic logic unit with mask generator.
Guttag Karl M. (Sugar Land TX) Balmer Keith (Bedford GB2) Gove Robert J. (Plano TX) Read Christopher J. (Houston TX) Golston Jeremiah E. (Sugar Land TX) Poland Sydney W. (Katy TX) Ing-Simmons Nichola, Three input arithmetic logic unit with mask generator.
Guttag Karl M. (Sugar Land TX) Balmer Keith (Bedford GB2) Gove Robert J. (Plano TX) Read Christopher J. (Houston TX) Golston Jeremiah E. (Sugar Land TX) Poland Sydney W. (Katy TX) Ing-Simmons Nichola, Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically ande.
Biggs Kent E. (Tomball TX) Lobodzinski Mark A. (Houston TX), Video driver system for communicating device specific primitive commands to multiple video controller types.
Fallon, James J.; Buck, John; Pickel, Paul F.; McErlain, Stephen J., Systems and methods for accelerated loading of operating systems and application programs.
Fallon, James J.; Buck, John; Pickel, Paul F.; McErlain, Stephen J., Systems and methods for accelerated loading of operating systems and application programs.
Fallon, James J.; Buck, John; Pickel, Paul F.; McErlain, Stephen J., Systems and methods for accelerated loading of operating systems and application programs.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.