IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0863866
(2001-05-23)
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우선권정보 |
JP-0153706 (2000-05-24); JP-0153707 (2000-05-24); JP-0153708 (2000-05-24); JP-0016866 (2001-01-25) |
발명자
/ 주소 |
- Okada, Satoru
- Yoneyama, Kazuo
- Ota, Masahiko
- Umezu, Ryuji
- Nakashima, Takanobu
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
15 인용 특허 :
70 |
초록
▼
An information processing device such as a game machine is selectively connectable to different peripheral devices such as memory devices. These peripheral devices may be provided with characteristics for distinguishing one from another. The information processing device carries out operations based
An information processing device such as a game machine is selectively connectable to different peripheral devices such as memory devices. These peripheral devices may be provided with characteristics for distinguishing one from another. The information processing device carries out operations based on the peripheral device connected thereto.
대표청구항
▼
1. An information processing device comprising an external bus having a first data width, and via the external bus, being engaged with, in a detachable manner, either a first cartridge which houses first memory having the first data width or a second cartridge which houses second memory having a sec
1. An information processing device comprising an external bus having a first data width, and via the external bus, being engaged with, in a detachable manner, either a first cartridge which houses first memory having the first data width or a second cartridge which houses second memory having a second data width different from the first data width, and executing processing based on data stored in the memory of whichever cartridge is selectively engaged, wherein,said second cartridge is provided with marker means to be distinguished from said first cartridge,said information processing device comprising:cartridge discrimination means for discriminating, based on said marker means, between said first cartridge and said second cartridge;central processing means for accessing the memory of the engaged cartridge;first access control means for controlling said external bus under a normal bus control method, and having said central processing unit access said first memory;second access control means for controlling said external bus under a bus control method different from the bus control method for said first access control means, and having said central processing means access said second memory; andselection means for selecting said first access control means when said cartridge discrimination means determines the engaged cartridge as being said first cartridge, and selecting said second access control means when the engaged cartridge is determined as being said second cartridge. 2. The information processing device as described in claim 1, wherein said second data width is wider than said first data width, andsaid second access control means exchanges address and data between said central processing means and said second memory by using said external bus in a time-sharing manner. 3. The information processing device as described in claim 2, wherein said second access control means controls, in the time-sharing manner, said external bus to be used with a first timing for an address signal and with a second timing for a data signal. 4. The information processing device as described in claim 1, whereinsaid marker means comprises a shape difference between said first cartridge and said second cartridge, andsaid cartridge discrimination means abuts the engaged cartridge, and based on said shape difference, identifies the engaged cartridge as being said first or second cartridge. 5. The information processing device as described in claim 2, wherein said second cartridge further houses third memory having said first data width,the information processing device further comprises determination means to determine, when said cartridge discrimination means identifies the engaged cartridge as being said second cartridge, which of said second memory and said third memory is to be accessed by said central processing means, andsaid second access control means controls said external bus in the time-sharing manner when said determination means determines said central processing means is to access said second memory, and controls said external bus under the normal bus control method when said determination means determines said central processing means is to access said third memory. 6. The information processing device as described in claim 5, whereinan address space for said central processing means to access said second memory is allocated to a first address space, and an address space for said central processing means to access said third memory is allocated to a second address space, andsaid determination means determines, when said first address space is designated, said second memory as being accessed, and when said second address space is designated, said third memory as being accessed. 7. The information processing device as described in claim 1, wherein said central processing means comprises:a first operation function operating in said first data width; anda second operation function operating in said second data width, andsaid select ion means selects said first operation function when said cartridge discrimination means determines the engaged cartridge as being said first cartridge, and selects said second operation function when the engaged cartridge is determined as being said second cartridge. 8. The information processing device as described in claim 1, wherein said second cartridge comprises:address retention means for retaining an address value outputted from said central processing means; andincrement means for incrementing the value retained by said address retention means in response to a control signal outputted from said central processing means, andby designating the value retained in said address retention means as an address value, sequential access is carried out. 9. The information processing device as described in claim 1, whereinsaid marker means comprises memory housed in said second cartridge for storing an identification code indicating a cartridge type, andsaid cartridge discrimination means reads out said identification code, and based on said identification code, identifies the engaged cartridge as being said first or second cartridge. 10. The information processing device as described in claim 1, whereinsaid marker means comprises two signal lines being either shorted or not-shorted, andsaid cartridge discrimination means detects whether said two signal lines are shorted or not-shorted, and based thereon, identifies the engaged cartridge as being said first or second cartridge. 11. A storage device being placed inside of a first cartridge engaged with an information processing device in a detachable manner, and storing data executed or utilized by the information processing device, wherein,said information processing device comprises a connector being engageable with, in a detachable manner, either said first cartridge whose bus has a first data width or a second cartridge whose bus has a second data width narrower than the first data width, and having the same data width as said second data width; and central processing means which accesses, when connected with said first or second cartridge via the connector, the first cartridge in a multiplex bus transfer mode, and the second cartridge in a normal bus transfer mode, said storage device comprising:general-purpose memory having said first data width for storing data to cause said central processing means to execute processing; andmultiplex bus conversion means for controlling, in a time-sharing manner, address and data exchange between said central processing means and said general-purpose memory. 12. The storage device as described in claim 11, wherein said multiplex bus conversion means comprises:address retention means for retaining an address value outputted from said central processing means;increment means for incrementing the value retained in said address retention means in response to a control signal outputted from said central processing means, andthe value retained in said address retention means is outputted to said general-purpose memory, and said central processing means is caused to carry out sequential access with respect to the general-purpose memory. 13. The storage device as described in claim 11, wherein said general-purpose memory and said multiplex bus conversion means are structured on one chip. 14. The storage device as described in claim 11, wherein the data width of said general-purpose memory is wider than memory housed in said second cartridge. 15. A cartridge engaged with an information processing device, in a detachable manner, via a connector having a first data width, the cartridge comprising:memory for storing data to cause said information processing device to execute processing, and having a second data width wider than said first data width;marker means for designating a method for accessing said memory as a multiplex method; andmultiplex bus conversion means for controlling, in a time-sharing manner, address and data exchange between said inf ormation processing device and said memory. 16. The cartridge as described in claim 15, wherein said marker means comprises a shape of a cartridge. 17. The cartridge as described in claim 15, wherein,in said information processing device, said connector is selectively engaged in a detachable manner with another cartridge which houses memory having said first data width. 18. The cartridge as described in claim 15, whereinsaid information processing device can select between a normal bus transfer mode and a multiplex bus transfer mode when accessing to the memory housed in the cartridge, andsaid marker means is used to let said information processing device select the multiplex bus transfer mode. 19. The cartridge as described in claim 17, whereinsaid information processing device includes a first operation function in said first data width, and a second operation function in said second data width, andsaid marker means is used to let said information processing device operate said second operation function. 20. The cartridge as described in claim 15, wherein said marker means stores an identification code indicating a cartridge type, and comprises memory housed in said second cartridge. 21. The cartridge as described in claim 15, wherein said marker means comprises two signal lines being either shorted or not-shorted. 22. A game system, comprising:a first game machine including a first central processing unit with low throughput;a first cartridge engageable with the first game machine in a detachable manner;a second game machine higher in performance than the first game machine and which is compatible with said first game machine; anda second cartridge engageable with the second game machine, wherein said first cartridge comprises:a first housing, said first housing accommodatinga first semiconductor information storage element fixedly storing game program data, and being accessible using a first data width, anda first circuit board, in a desired circuit pattern, having a plurality of terminals formed on one side thereof, and the first semiconductor information storage element being mounted thereon,said second cartridge comprises:a second housing having a to-be-detected part for distinction from the first cartridge;a second semiconductor information storage element for fixedly storing game program data, and being accessible using a second data width wider than said first data width;a second circuit board, in a desired circuit pattern, having the same number of terminals in the same alignment formed on one side thereof as said first circuit board; andmultiaccess control means for reading the game program data stored in said second semiconductor information storage element in the multiplex system, said second housing accommodating said second semiconductor information storage element and the multiaccess control means both mounted on said second circuit board, andsaid second game machine comprises:a connector for establishing electrical connection with said second cartridge having the same number of terminals in the same alignment as another connector provided in said first game machine so that said first cartridge becomes engageable;a second central processing unit with higher throughput compared with said first central processing unit;a third central processing unit having about the same throughput as said first central processing unit;first access control means for accessing said first cartridge;second access control means for accessing said second cartridge in a multiplex system; anddetection means for detecting said to-be-detected part provided to said second housing, whereinwhen said detection means detects said to-be-detected part, said second central processing unit and said second access control means are activated to access said second cartridge, and said multiaccess control means accesses said second semiconductor information storage element, andwhen said detection means does not detect said to-be-detected part, said th ird central processing unit and said first access control means are activated to access said first cartridge. 23. The game system as described in claim 22, whereinsaid first semiconductor information storage element outputs data of a first number of data bits, andsaid second semiconductor information storage element outputs data of a second number of data bits larger than said first number of data bits. 24. The game system as described in claim 22, whereinsaid first semiconductor information storage element is accessed by address data of a first number of address bits, andsaid second semiconductor information storage element is accessed by address data of a second number of address bits larger than said first number of address bits. 25. The game system as described in claim 22, wherein said second housing is structured to be shorter in height than said first housing, and on one side plane not inserted into said second game machine, a protrusion is so formed as to protrude at least to one lateral direction. 26. The game system as described in claim 22, wherein said multiaccess control means is integrally formed on a chip together with said second semiconductor information storage element, and electrically placed in between said second semiconductor information storage element and a lead terminal connected to the plurality of terminals in the circuit pattern of said circuit board. 27. The game system as described in claim 22, wherein, when accessed by said second central processing unit, said multiaccess control means acquires a desired address of said second semiconductor information storage element with a first timing to access the second semiconductor information storage element and read information therefrom, and with a second timing, supplies data read from the second semiconductor information storage element to said second game machine. 28. The game system as described in claim 22, whereinsaid second semiconductor information storage element is driven by a second driving voltage different from a first driving voltage for said first semiconductor information storage element, andafter cartridge insertion, said second game machine supplies the first driving voltage to the first cartridge and the second driving voltage to the second cartridge so that the first and the second cartridges both are selectively usable. 29. A game cartridge used as a second cartridge in a game system comprising:a first game machine low in performance;a first cartridge engageable with the first game machine in a detachable manner;a second game machine being higher in performance than the first game machine, and having compatibility with the first game machine; andsaid second cartridge engageable with the second game machine in a detachable manner, whereinsaid second cartridge comprises:a housing;a to-be-detected part formed in said housing for distinction from said first cartridge;a second semiconductor information storage element housed in said housing for fixedly storing game program data for said second game machine and being accessed by a data width wider than that of a first semiconductor information storage element included in said first cartridge;multiaccess control means for reading the game program data stored in said second semiconductor information storage element in a multiplex system; anda circuit board, whereinsaid circuit board has the same number of terminals in the same alignment formed on one side thereof as in said first cartridge, and when said second semiconductor information storage element and said multiaccess control means are mounted thereon, a desired circuit pattern is so established as to connect among the terminals, the second semiconductor information storage element, and the multiaccess control means. 30. The game cartridge as described in claim 29, wherein data outputted by said second semiconductor information storage element is larger in number of data bits than data outputted by the first semiconductor information s torage element included in said first cartridge. 31. The game cartridge as described in claim 29, wherein the number of address bits accessing said second semiconductor information storage element is larger than the number of address bits accessing said first semiconductor information storage element. 32. The game cartridge as described in claim 29, wherein said housing of said second cartridge is structured to be shorter in height than said first cartridge for said first game machine, and on one side plane not inserted into said second game machine, a protrusion is so formed as to protrude at least to one lateral direction. 33. The game cartridge as described in claim 29, wherein said multiaccess control means is integrally formed on a chip together with said second semiconductor information storage element, and placed in between said second semiconductor information storage element and a terminal part connected to the plurality of terminals in the circuit pattern of said circuit board. 34. The game cartridge as described in claim 29, wherein, when accessed by processing means included in said second game machine, said multiaccess control means designates a desired address of said second semiconductor information storage element by address data of address bits larger in number than address bits of said first semiconductor information storage element, and reads data of the designated address by using address terminals for a lower number of bit address data for supply to said second game machine. 35. The game cartridge as described in claim 29, whereinsaid second semiconductor information storage element is driven by a driving voltage different from that for said first semiconductor information storage element, andsaid circuit board of said second cartridge includes a power-supply terminal for receiving, from said second game machine, a voltage supply different from that from said first game machine. 36. The game cartridge as described in claim 29, wherein said multiaccess control means comprises address retention means for retaining an address value, and the address retention means is so structured as to acquire an address value on a bus in response to a first signal, and increment data of said address retention means in response to a second signal. 37. A game machine used as a second game machine in a game system comprising:a first game machine including a first central processing unit with low throughput;a first cartridge engageable with the first game machine in a detachable manner;the second game machine higher in performance than the first game machine and which is compatible with the first game machine; anda second cartridge engageable with the second game machine, wherein said first cartridge comprisesa first housing, said first housing accommodatinga first semiconductor information storage element fixedly storing game program data, and being accessible using a first data width, anda first circuit board, in a desired circuit pattern, having a plurality of terminals formed on one side thereof, and the first semiconductor information storage element being mounted thereon,said second cartridge comprises:a second housing having a to-be-detected part for distinction from the first cartridge;a second semiconductor information storage element for fixedly storing game program data, and being accessible using a second data width wider than said first data width;a second circuit board, in a desired circuit pattern, having the same number of terminals in the same alignment formed on one side thereof as said first circuit board; andmultiaccess control means for reading the game program data stored in said second semiconductor information storage element in the multiplex system, said second housing accommodatingsaid second semiconductor information storage element and the multiaccess control means both mounted on said second circuit board, andsaid game machine comprises:a connector for establishing electrical connection with said se cond cartridge having the same number of terminals in the same alignment as another connector provided in said first game machine so that said first cartridge becomes engageable;a second central processing unit with higher throughput compared with said first central processing unit;a third central processing unit having about the same throughput as said first central processing unit;first access control means for accessing said first cartridge;second access control means for accessing said second cartridge in a multiplex system; anddetection means for detecting said to-be-detected part provided to said second housing, whereinwhen said detection means detects said to-be-detected part, said second central processing unit and said second access control means are activated to access said second cartridge, and said multiaccess control means accesses said second semiconductor information storage element, andwhen said detection means does not detect said to-be-detected part, said third central processing unit and said first access control means are activated to access said first cartridge. 38. The game machine as described in claim 37, whereinsaid first semiconductor information storage element outputs data of a first number of data bits, andsaid second semiconductor information storage element outputs data of a second number of data bits larger than said first number of data bits. 39. The game machine as described in claim 37, whereinsaid first semiconductor information storage element is accessed by address data of a first number of address bits, andsaid second semiconductor information storage element is accessed by address data of a second number of address bits larger than said first number of address bits. 40. The game machine as described in claim 37, whereinsaid second semiconductor information storage element is so selected as to be driven by a second driving voltage different from a first driving voltage for said first semiconductor information storage element, andwhen said detection means detects said to-be-detected part, the second driving voltage is supplied to the second cartridge, and when said detection means does not detect said to-be-detected part, the first driving voltage is supplied to the first cartridge. 41. An information processing device comprising an external bus having a first data width, and via the external bus, being engaged with, in a detachable manner, either a first cartridge which houses first memory having the first data width or a second cartridge which houses second memory having a second data width different from the first data width, and executing processing based on data stored in the memory of whichever cartridge is selectively engaged, wherein,said second cartridge is provided with a marker to be distinguished from said first cartridge,said information processing device comprises:a cartridge discriminator for discriminating, based on said marker, between said first cartridge and said second cartridge;a central processing unit for accessing the memory of the engaged cartridge;a first access controller for controlling said external bus under a normal bus control method, and having said central processing unit access said first memory;a second access controller for controlling said external bus under a bus control method different from the bus control method for said first access controller, and having said central processing unit access said second memory; anda selector for selecting said first access controller when said cartridge discriminator determines the engaged cartridge as being said first cartridge, and selecting said second access controller when the engaged cartridge is determined as being said second cartridge. 42. A storage device being placed inside of a first cartridge engaged with an information processing device in a detachable manner, and storing data executed or utilized by the information processing device, wherein,said information processing device comprises a connector be ing engageable with, in a detachable manner, either said first cartridge whose bus has a first data width or a second cartridge whose bus has a second data width narrower than the first data width, and having the same data width as said second data width; and a central processing unit which accesses, when connected with said first or second cartridge via the connector, the first cartridge in a multiplex bus transfer mode, and the second cartridge in a normal bus transfer mode, andsaid storage device comprises:memory having said first data width for storing data to cause said central processing means to execute processing; anda multiplex bus converter for controlling, in a time-sharing manner, address and data exchange between said central processing unit and said memory.
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