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Reduced-overhead DMA 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0474499 (2002-04-11)
국제출원번호 PCT/US02/11582 (2002-04-11)
국제공개번호 WO02/08449 (2002-10-24)
발명자 / 주소
  • Stadler, Mark
  • Eiriksson, Asgeir Thor
  • Naghshineh, Kianoosh
출원인 / 주소
  • Chelsio Communications, Inc.
대리인 / 주소
    Morrison & Foerster LLP
인용정보 피인용 횟수 : 27  인용 특허 : 12

초록

A plurality of direct memory access data transfers are accomplished to transfer data from a host to an adaptor. For each transfer, an indication of locations of at least one group of storage locations associated with the host available to hold the data to be transferred to the host is provided from

대표청구항

1. A method for accomplishing a plurality of direct memory access data transfers from a host to an adaptor, comprising:for each transfer,providing, from the host to the adaptor, an indication of locations of at least one group of storage locations associated with the host holding the data to be tran

이 특허에 인용된 특허 (12)

  1. Wilcox Jeffrey, Address triggered DMA controller with an indicative signal including circuitry for calculating a new trigger address value based on the sum of the current trigger address and the descriptor register .
  2. Baldwin David R. (Sheppston GBX) Sata Shingo (Otawara JPX), Apparatus for detecting and correcting data transfer errors of a magnetic disk system.
  3. Nishikawa Junji,JPX, DMA-transferring stream data apparatus between a memory and ports where a command list includes size and start address o.
  4. Morioka Yoshihiro,JPX ; Motomura Naohisa,JPX ; Kase Hiroshi,JPX ; Hamai Shinji,JPX, Data recorder and method of access to data recorder.
  5. Bowes Michael J. ; Childers Brian A., Dual bus concurrent multi-channel direct memory access controller and method.
  6. Olson Steven E. ; Shaw Jhy-Ping, High speed dynamic chaining of DMA operations without suspending a DMA controller or incurring race conditions.
  7. Futral William T. ; Bell D. Michael, Method and apparatus for programming a remote DMA engine residing on a first bus from a destination residing on a second bus.
  8. Miura Katsumi (Tokyo JPX) Mitsuhira Yuko (Tokyo JPX), Microcomputer equipped with DMA controller allowed to continue to perform data transfer operations even after completion.
  9. Reid Richard ; Sherer William Paul ; Connery Glenn, Network and adaptor with time-based and packet number based interrupt combinations.
  10. Story Franklyn H. ; Evoy David R. ; Chambers Peter ; Goff Lonnie, System for implementing peripheral device bus mastering in a computer using a list processor for asserting and receivin.
  11. Gephardt Douglas D. (Austin TX) Mudgett Dan S. (Austin TX) MacDonald James R. (Buda TX), System for performing I/O access and memory access by driving address of DMA configuration registers and memory address.
  12. Blumer Marc ; Ando Wayne, System for transferring input/output data independently through an input/output bus interface in response to programmab.

이 특허를 인용한 특허 (27)

  1. Louzoun, Eliel; Ben-Shahar, Yifat, Communication between two embedded processors.
  2. Naghshineh, Kianoosh; Stadler, Mark D.; Eiriksson, Asgeir Thor, Configurable switching network interface controller using forwarding engine.
  3. Eiriksson, Asgeir Thor; Mao, Chris Yuhong, Filtering ingress packets in network interface circuitry.
  4. Singer, Eric L., Four-slot asynchronous communication mechanism with decreased latency.
  5. Cummings, Rodney W.; Singer, Eric L., Four-slot asynchronous communication mechanism with increased throughput.
  6. Noureddine, Wael; Eiriksson, Asgeir Thor, Full offload of stateful connections, with partial connection offload.
  7. Michailidis, Dimitrios; Noureddine, Wael; Marti, Felix A.; Eiriksson, Asgeir Thor, Intelligent network adaptor with adaptive direct data placement scheme.
  8. Michailidis, Dimitrios; Noureddine, Wael; Marti, Felix A.; Eiriksson, Asgeir Thor, Intelligent network adaptor with end-to-end flow control.
  9. Michailidis, Dimitrios; Noureddine, Wael; Marti, Felix A.; Eiriksson, Asgeir Thor, Intelligent network adaptor with end-to-end flow control.
  10. Eiriksson, Asgeir Thor; Noureddine, Wael, Method for UDP transmit protocol offload processing with traffic management.
  11. Eiriksson, Asgeir Thor; Noureddine, Wael; Mao, Chris Yuhong, Method for traffic schedulign in intelligent network interface circuitry.
  12. Eiriksson, Asgeir Thor; Noureddine, Wael; Mao, Chris Yuhong, Method for traffic scheduling in intelligent network interface circuitry.
  13. Eiriksson, Asgeir Thor; Noureddine, Wael, Method to implement an L4-L7 switch using split connections and an offloading NIC.
  14. Eiriksson, Asgeir Thor; Noureddine, Wael, Method to implement an L4-L7 switch using split connections and an offloading NIC.
  15. Naghshineh,Kianoosh; Stadler,Mark; Eiriksson,Asgeir Thor, Multi-purpose switching network interface controller.
  16. Eiriksson, Asgeir Thor; Srinivasaiah, Chandrasekhar; Noureddine, Wael, Network adaptor configured for connection establishment offload.
  17. Eiriksson, Asgeir Thor; Srinivasaiah, Chandrasekhar; Noureddine, Wael, Network adaptor configured for connection establishment offload.
  18. Trainin, Solomon B., Network interface with transmit frame descriptor reuse.
  19. Michailidis, Dimitrios; Noureddine, Wael; Marti, Felix A.; Eiriksson, Asgeir Thor, Protocol offload in intelligent network adaptor, including application level signalling.
  20. Eiriksson, Asgeir Thor; Noureddine, Wael; Mao, Chris Yuhong, Protocol offload transmit traffic management.
  21. Eiriksson, Asgeir Thor; Noureddine, Wael; Mao, Chris Yuhong, Protocol offload transmit traffic management.
  22. Eiriksson, Asgeir Thor; Noureddine, Wael; Mao, Chris Yuhong, Protocol offload transmit traffic management.
  23. Eiriksson, Asgeir Thor; Chen, Shenze; Kaplan, Patricio Fernando; Smith, George E., Scalable direct memory access using validation of host and scatter gather engine (SGE) generation indications.
  24. Cummings, Rodney W.; Pitts, William R.; Brzezinski, Matthew M.; Singer, Eric L., Single point, device driven data transmission for a real time application.
  25. Henson,Matthew; Baker,David Cureton, System and method for communicating with memory devices via plurality of state machines and a DMA controller.
  26. Eiriksson, Asgeir Thor; Michailidis, Dimitrios; Noureddine, Wael, Virtualizing the operation of intelligent network interface circuitry.
  27. Eiriksson, Asgeir Thor; Michailidis, Dimitrios; Noureddine, Wael, Virtualizing the operation of intelligent network interface circuitry.
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