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In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or fir

In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.

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1. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate; andcreating a patterned layer of ONO over areas of said substrate that must be shielded from process of salicidation, said creating a patterned layer of ON

1. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate; andcreating a patterned layer of ONO over areas of said substrate that must be shielded from process of salicidation, said creating a patterned layer of ONO comprising:(i) patterning an upper or first layer of silicon dioxide by applying a wet-etch to the upper or first layer of silicon dioxide;(ii) patterning a central layer of silicon nitride, using the patterned first layer of silicon dioxide as a hardmask, by applying a wet nitride removal process to the layer of silicon nitride; and(iii) patterning a lower or second layer of silicon dioxide, using the patterned first layer of silicon dioxide and the patterned central layer of silicon nitride as a mask, by applying a wet-etch to the lower of second layer of silicon oxide. 2. The method of claim 1, said layer of ONO comprising:a first layer of silicon dioxide deposited over said substrate;a layer of silicon nitride deposited over said first layer of silicon dioxide; anda second layer of silicon dioxide deposited over said layer of silicon nitride. 3. The method of claim 2, said first layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 4. The method of claim 2, said layer of silicon nitride being deposited to a thickness of about 250 Angstrom. 5. The method of claim 2, said second layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 6. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate; andcreating a patterned layer of ONO over areas of said substrate that must be shielded from process of salicidation, said patterned layer of ONO comprising;(i) a first layer of silicon dioxide deposited over said substrate;(ii) a layer of silicon nitride deposited over said first layer of silicon dioxide; and(iii) a second layer of silicon dioxide deposited over said layer of silicon nitride;said creating a patterned layer of ONO comprising:(a) patterning the first layer of silicon dioxide by applying a wet-etch to the first layer of silicon dioxide;(b) patterning the layer of silicon nitride, using the patterned first layer of silicon dioxide as a hardmask, by applying a wet nitride removal process to the layer of silicon nitride; and(c) patterning the second layer of silicon dioxide, using the patterned first layer of silicon dioxide and the patterned central layer of silicon nitride as a mask by applying a wet-etch to the second layer of silicon oxide. 7. The method of claim 6, said first layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 8. The method of claim 6, said layer of silicon nitride being deposited to a thickness of about 250 Angstrom. 9. The method of claim 6, said second layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 10. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate; andcreating by applying methods of wet etch a patterned layer of ONO over areas of said substrate that must be shielded from process of salicidation, said patterned layer of ONO comprising:(i) a first layer of silicon dioxide deposited over said substrate;(ii) a layer of silicon nitride deposited over said first layer of silicon dioxide; and(iii) a second layer of silicon dioxide deposited over said layer of silicon nitride;said creating a patterned layer of ONO comprising:(a) patterning the first layer of silicon dioxide by applying a wet-etch to the first layer of silicon dioxide;(b) patterning the layer of silicon nitride, using the patterned first layer of silicon dioxide as a hardmask, by applying a wet nitride removal process to the layer of silicon nitride; and(c) patterning the second layer of silicon dioxide, using the patterned first layer of silicon dioxide and the patte rned central layer of silicon nitride as a mask, by applying a wet-etch to the lower of second layer of silicon oxide. 11. The method of claim 10, said first layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 12. The method of claim 10, said layer of silicon nitride being deposited to a thickness of about 250 Angstrom. 13. The method of claim 10, said second layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 14. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate; andcreating by applying methods of wet etch a patterned layer of ONO over areas of said substrate that must be shielded from process of salicidation, said patterned layer of ONO comprising:(i) a first layer of silicon dioxide deposited over said substrate, said first layer of silicon dioxide being deposited to a thickness of about 80 Angstrom;(ii) a layer of silicon nitride deposited over said first layer of silicon dioxide, said layer of silicon nitride being deposited to a thickness of about 250 Angstrom; and(iii) a second layer of silicon dioxide deposited over said layer of silicon nitride, said second layer of silicon dioxide being deposited to a thickness of about 80 Angstrom;said creating by applying methods of wet etch a patterned layer of ONO comprising:(a) patterning the first layer of silicon dioxide by applying a wet-etch to the first layer of silicon dioxide;(b) patterning the layer of silicon nitride, using the patterned first layer of silicon dioxide as a hardmask, by applying a wet nitride removal process to the layer of silicon nitride; and(c) patterning the second layer of silicon dioxide, using the patterned first layer of silicon dioxide and the patterned central layer of silicon nitride as a mask, by applying a wet-etch to the second layer of silicon oxide. 15. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate, a first and a second region having been defined over said substrate, said first region being a region comprising at least one CMOS device to which no process of salicidation of contact surfaces thereof is to be provided, said second region being a region comprising at least one CMOS device to which salicidation of contact surfaces thereof is to be provided; andcreating a patterned layer of Resist Protect Oxide (RPO) over said first area of said substrate, said creating a patterned layer of RPO comprising:(a) patterning a first layer of silicon dioxide by applying a wet-etch to the first layer of silicon dioxide;(b) patterning a layer of silicon nitride, using the patterned first layer of silicon dioxide as a hardmask, by applying a wet nitride removal process to the layer of silicon nitride; and(c) patterning a second layer of silicon dioxide, using the patterned first layer of silicon dioxide and the patterned central layer of silicon nitride as a mask by applying a wet-etch to second layer of silicon dioxide. 16. The method of claim 15, said patterned—layer of Resist Protect Oxide comprising:a first layer of silicon dioxide deposited over said substrate;a layer of silicon nitride deposited over said first layer of silicon dioxide; anda second layer of silicon dioxide deposited over said layer of silicon nitride. 17. The method of claim 16, said first layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 18. The method of claim 16, said layer of silicon nitride being deposited to a thickness of about 250 Angstrom. 19. The method of claim 16, said second layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 20. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate, a first and a second region having been defined over said substrate, said first region being a region compr ising at least one CMOS device to which no process of salicidation of contact surfaces thereof is to be provided, said second region being a region comprising at least one CMOS device to which salicidation of contact surfaces thereof is to be provided; andcreating a patterned layer of Resist Protect Oxide (RPO) over said first area of said substrate, said patterned layer of Resist Protect Oxide comprising:(i) a first layer of silicon dioxide deposited over said substrate;(ii) a layer of silicon nitride deposited over said first layer of silicon dioxide; and(iii) a second layer of silicon dioxide deposited over said layer of silicon nitride;said creating a patterned layer of RPO comprising:(a) patterning the first layer of silicon dioxide by applying a wet-etch to the first layer of silicon dioxide;(b) patterning the layer of silicon nitride, using the patterned first layer of silicon dioxide as a hardmask, by applying a wet nitride removal process to the layer of silicon nitride; and(c) patterning the second layer of silicon dioxide, using the patterned first layer of silicon dioxide and the patterned central layer of silicon nitride as a mask, by applying a wet-etch to the second layer of silicon dioxide. 21. The method of claim 20, said first layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 22. The method of claim 20, said layer of silicon nitride being deposited to a thickness of about 250 Angstrom. 23. The method of claim 20, said second layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 24. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate, a first and a second region having been defined over said substrate, said first region being a region comprising at least one CMOS device to which no process of salicidation of contact surfaces thereof is to be provided, said second region being a region comprising at least one CMOS device to which salicidation of contact surfaces thereof is to be provided; andcreating by applying methods of wet etch a patterned layer of Resist Protect Oxide (RPO) over said first area of said substrate, said patterned layer of Resist Protect Oxide comprising:(i) a first layer of silicon dioxide deposited over said substrate;(ii) a layer of silicon nitride deposited over said first layer of silicon dioxide; and(iii) a second layer of silicon dioxide deposited over said layer of silicon nitride;said creating by applying methods of wet etch a patterned layer of RPO comprising:(a) patterning the first layer of silicon dioxide by applying a wet-etch to the first layer of silicon dioxide;(b) patterning the layer of silicon nitride, using the patterned first layer of silicon dioxide as a hardmask, by applying a wet nitride removal process to the layer of silicon nitride; and(c) patterning the second layer of silicon dioxide, using the patterned first layer of silicon dioxide and the patterned central layer of silicon nitride as a mask by applying a wet-etch to the second layer of silicon dioxide. 25. The method of claim 24, said first layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 26. The method of claim 24, said layer of silicon nitride being deposited to a thickness of about 250 Angstrom. 27. The method of claim 24, said second layer of silicon dioxide being deposited to a thickness of about 80 Angstrom. 28. A method for forming Resist Protect Oxide (RPO) applied for sub-micron salicidation, comprising steps of:providing a semiconductor substrate, a first and a second region having been defined over said substrate, said first region being a region comprising at least one CMOS device to which no process of salicidation of contact surfaces thereof is to be provided, said second region being a region comprising at least one CMOS device to which salicidation of contact surfaces thereof is to be provided; andcreating by applying methods of wet etch a patterned layer of Resist Protect Oxide (RPO) over said first area of said substrate, said patterned layer of Resist Protect Oxide comprising:(i) a first layer of silicon dioxide deposited over said substrate, said first layer of silicon dioxide being deposited to a thickness of about 80 Angstrom;(ii) a layer of silicon nitride deposited over said first layer of silicon dioxide, said layer of silicon nitride being deposited to a thickness of about 250 Angstrom; and(iii) a second layer of silicon dioxide deposited over said layer of silicon nitride, said second layer of silicon dioxide being deposited to a thickness of about 80 Angstrom;said creating by applying methods of wet etch a patterned layer of RPO comprising:(a) patterning the first layer of silicon dioxide by applying a wet-etch to the first layer of silicon dioxide;(b) patterning the layer of silicon nitride, using the patterned first layer of silicon dioxide as a hardmask, by applying a wet nitride removal process to the layer of silicon nitride; and(c) patterning the second layer of silicon dioxide, using the patterned first layer of silicon dioxide and the patterned central layer of silicon nitride as a mask, by applying a wet-etch to the second layer of silicon dioxide.