초록

The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

대표청구항 ▼

1. A method of forming portions of circuits connected to bond pads of a semiconductor device, said semiconductor device having circuitry, having at least one surface, and having at least a portion of a circuit on a portion of said at least one surface of said semiconductor device connected to a port

1. A method of forming portions of circuits connected to bond pads of a semiconductor device, said semiconductor device having circuitry, having at least one surface, and having at least a portion of a circuit on a portion of said at least one surface of said semiconductor device connected to a portion of said circuitry and terminating in a bond pad, said at least a portion of said circuit having a portion thereof covered by a first passivation layer while said bond pad remains substantially free of said first passivation layer, said method comprising:forming a trace of solder wettable material from said bond pad of said circuit to another location on said at least one surface of said semiconductor device, said trace of said solder wettable material contacting a portion of said bond pad and extending over a portion of said first passivation layer, said trace of said solder wettable material having a first surface and a second surface, a portion of said second surface contacting said bond pad;forming a second passivation layer over said portion of said at least one surface of said semiconductor device and said trace of said solder wettable material; andremoving a portion of said second passivation layer to form a sloped-wall via through said second passivation layer extending to a portion of said first surface of said trace of solder wettable material at said another location on said at least one surface of said semiconductor device. 2. The method of claim 1, wherein said removing includes an etching process selected from a group comprising sputter etching and wet etching. 3. The method of claim 2, wherein said etching comprises sputter etching after application of a resist layer over said second passivation layer, said resist layer having an aperture therein aligned with said another location on said at least one surface of said semiconductor device. 4. The method of claim 1, further comprising:depositing a solder mass over said sloped-wall via. 5. The method of claim 4, further comprising:liquefying said solder mass and cooling said solder mass to define a solder ball or bump. 6. The method of claim 1, wherein said circuit is selected from a group consisting of bond pads and conductive traces. 7. A metallization forming method for a semiconductor device, said semiconductor device having circuitry and having at least one surface, said semiconductor device including at least a portion of a solder wettable trace on at least a portion of said at least one surface connected to at least a portion of said circuitry, said semiconductor device having at least one passivation layer over at least a portion of said portion of said solder wettable trace on said at least a portion of said at least one surface, said method comprising: removing a portion of said at least one passivation layer for forming a sloped-wall via; and exposing a portion of said solder wettable trace. 8. The method of claim 7, wherein said removing a portion of said at least one passivation layer for forming said sloped-wall via comprises etching. 9. The method of claim 8, wherein said etching is selected from a group consisting of sputter etching and wet etching. 10. The method of claim 8, wherein said etching comprises sputter etching after application of a resist layer over said at least one passivation layer, said resist layer having an aperture therein aligned with said at least a portion of said solder wettable trace on said at least a portion of said at least one surface of said semiconductor device. 11. The method of claim 8, wherein said etching comprises wet etching effected after application of a resist layer over said at least one passivation layer, said resist layer having an aperture therein aligned with said at least a portion of said solder wettable trace on said at least a portion of said at least one surface of said semiconductor device. 12. A manufacturing method for a semiconductor device, said semiconductor device having integrated circuitry and a portion of a trace connected to said integrated circuitry, said trace having a bond pad connected thereto, said method comprising:forming at least one first passivation layer over a portion of said trace while said bond pad remains substantially free of said at least one first passivation layer;forming another trace in contact with at least a portion of said bond pad, a portion of said another trace extending over a portion of said at least one first passivation layer, said another trace having an upper surface;forming a second passivation layer over a portion of said trace;removing a portion of said second passivation layer for forming a portion of a sloped-wall via through said second passivation layer extending to a portion of said upper surface of said another trace; andforming a solder mass having a portion thereof extending into said sloped-wall via contacting said portion of said upper surface of said another trace. 13. The manufacturing method of claim 12, wherein said another trace comprises a solder wettable material. 14. The manufacturing method of claim 13, wherein said solder wettable material comprises copper, nickel, palladium, platinum, gold, or an alloy thereof. 15. The manufacturing method of claim 14, wherein one of said portion of said trace and said at least a portion of said bond pad comprises copper, nickel, palladium, platinum, gold or an alloy thereof.