IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0328203
(2002-12-23)
|
발명자
/ 주소 |
- Sabbavarapu, Anil K.
- Jaber, Talal K.
- McFarland, Grant W.
- Sunkerneni, Paven R.
- Wu, David M.
|
출원인 / 주소 |
|
대리인 / 주소 |
Buckley, Maschoff & Talwalkar LLC
|
인용정보 |
피인용 횟수 :
39 인용 특허 :
3 |
초록
▼
According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to t
According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.
대표청구항
▼
1. A circuit comprising:a Domino state element to receive a data signal;a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal; anda slave latch to receive a second clock signal and to output the value in response to the
1. A circuit comprising:a Domino state element to receive a data signal;a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal; anda slave latch to receive a second clock signal and to output the value in response to the second clock signals,wherein the Domino state element is to receive a third clock signal,and wherein the data signal is to be active and the third clock signal is to be inactive when the master latch is to store the value and when the slave latch is to output the value. 2. A circuit according to claim 1, wherein the slave latch comprises a full static keeper. 3. A circuit according to claim 2, wherein the slave latch further comprises a pass gate to pass a second value to the full static keeper in response to the second clock signal, the second value to represent the value. 4. A circuit according to claim 1, wherein the master latch comprises a first input to receive the value and a second input to receive the first clock signal. 5. A circuit according to claim 4, wherein the slave latch further comprises a pass gate to pass the value to a storage node in response to the second clock signal. 6. A circuit according to claim 1, further comprising:a first combinational logic block coupled to the Domino state element and to receive a third clock signal,wherein the Domino state element is to receive the third clock signal and to store a second value generated by the first combinational logic block. 7. A circuit according to claim 6, further comprising:a second Domino state element to receive a fourth clock signal;a second master latch to receive the first clock signal and to store a third value in the second Domino state element in response to the first clock signal;a second slave latch to receive the second clock signal and to output the third value in response to the second clock signal; anda second combinational logic block coupled to the first Domino state element and to the second Domino state element, and to receive the fourth clock signal,wherein the fourth clock signal is a complement of the third clock signal. 8. A method comprising:applying an active slave clock signal to a slave latch coupled to a Domino state element to output a first value stored in the Domino state element;applying an active master clock signal to a master latch coupled to the Domino state element to store a second value in the Domino state element; andapplying, during the step of applying the active master clock signal to the master latch, a scan value signal representing the second value to the master latch while applying an active data signal to a data terminal of the Domino state element and applying an inactive clock signal to a clock terminal of the Domino state element. 9. A method according to claim 8, further comprising:applying the active slave clock signal to the slave latch to output the second value. 10. A method according to claim 8, further comprising:applying an active data signal to a data terminal of the Domino state element and applying an inactive clock signal to a clock terminal of the Domino state element during the step of applying the active master clock signal to the master latch and the step of applying the active slave clock signal to the slave latch. 11. A circuit comprising:a first state element coupled to a first node;a master scan cell coupled to the first state element, the master scan cell to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, the master scan cell to receive a first value from the first scan value signal and to store the first value at the first node in response to the first storage signal and the first clock signal;a second state element coupled to a second node, the second node sequential to the first node; anda slave scan cell coupled to the second state element, the slave scan cell to receive a second storage signal, a second load signal, a second clo ck signal and a second scan value signals, the slave scan cell to receive a second value from the second scan value signal and to store the second value at the second node in response to the second storage signal and the second clock signal. 12. A circuit according to claim 11, wherein the master scan cell loads a first value stored by the first state element into a scan chain in response to the first load signal, andwherein the slave scan cell loads a second value stored by the second state element into the scan chain in response to the second load signal. 13. A circuit according to claim 11, wherein the circuit comprises a hold scan cell. 14. A system comprising:a chipset; anda die comprising a microprocessor in communication with the chipset, wherein the microprocessor includes a circuit comprising:a Domino state element;a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal; anda slave latch to receive a second clock signal and to output the value in response to the second clock signals,wherein the Domino state element is to receive a data signal and a third clock signal,and wherein the data signal is to be active and the third clock signal is to be inactive when the master latch is to store the value and when the slave latch is to output the value. 15. A system according to claim 14, wherein the slave latch comprises a full static keeper. 16. A system according to claim 15, wherein the slave latch further comprises a pass gate to pass a second value to the full static keeper in response to the second clock signal, the second value to represent the value. 17. A system according to claim 14, the circuit further comprising:a first combinational logic block coupled to the Domino state element and to receive a third clock signal,wherein the Domino state element is to receive the third clock signal and to store a second value generated by the first combinational logic block. 18. A system according to claim 17, the circuit further comprising:a second Domino state element to receive a fourth clock signal;a second master latch to receive the first clock signal and to store a third value in the second Domino state element in response to the first clock signal;a second slave latch to receive the second clock signal and to output the third value in response to the second clock signal; anda second combinational logic block coupled to the first Domino state element and to the second Domino state element, and to receive the fourth clock signal,wherein the fourth clock signal is a complement of the third clock signal. 19. A system comprising:a chipset; anda die comprising a microprocessor in communication with the chipset, wherein the microprocessor includes a circuit comprising:a first state element coupled to a first node;a master scan cell coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, the master scan cell to receive a first value from the first scan value signal and to store the first value at the first node in response to the first storage signal and the first clock signal;a second state element coupled to a second node, the second node sequential to the first node; anda slave scan cell coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal, the slave scan cell to receive a second value from the second scan value signal and to store the second value at the second node in response to the second storage signal and the second clock signal. 20. A system according to claim 19, wherein the master scan cell loads a first value stored by the first state element into a scan chain in response to the first load signal, andwherein the slave scan cell loads a second value stored by the second state element into the scan chain in response to the seco nd load signal.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.