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Semiconductor integrated circuit device and a method of manufacturing the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0850162 (2001-05-08)
우선권정보 JP-0135041 (2000-05-08)
발명자 / 주소
  • Saito, Tatsuyuki
  • Ohashi, Naohumi
  • Imai, Toshinori
  • Noguchi, Junji
  • Tamaru, Tsuyoshi
출원인 / 주소
  • Renesas Technology Corp.
대리인 / 주소
    Antonelli, Terry, Stout & Kraus, LLP
인용정보 피인용 횟수 : 32  인용 특허 : 19

초록

A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for

대표청구항

1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:(a) forming a groove for wiring in a first insulating film formed on a semiconductor substrate;(b) successively forming a barrier layer and a conductive film over said first insulating film including the

이 특허에 인용된 특허 (19)

  1. Leon Ashley ; Hormazdyar M. Dalal ; Du Binh Nguyen ; Hazara S. Rathore ; Richard G. Smith, Copper interconnections with enhanced electromigration resistance and reduced defect sensitivity and method of forming same.
  2. Omura Masayoshi,JPX, Damascene wiring with flat surface.
  3. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
  4. Gruening Ulrike,DEX ; Divakaruni Ramachandra ; Mandelman Jack A. ; Rupp Thomas S., Embedded vertical DRAM cells and dual workfunction logic gates.
  5. Chen Lai-Juh,TWX, Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates.
  6. Grill Alfred ; Jahnes Christopher Vincent ; Patel Vishnubhai Vitthalbhai ; Saenger Katherine Lynn, Method and material for integration of fuorine-containing low-k dielectrics.
  7. Uozumi Yoshihiro,JPX, Method of forming a copper oxide film to etch a copper surface evenly.
  8. Daniel C. Edelstein ; Timothy J. Dalton ; John G. Gaudiello ; Mahadevaiyer Krishnan ; Sandra G. Malhotra ; Maurice McGlashan-Powell ; Eugene J. O'Sullivan ; Carlos J. Sambucetti, Method of forming barrier layers for damascene interconnects.
  9. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
  10. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
  11. Robinson Karl M. ; Walker Michael A., Polishing pad and method of use.
  12. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias.
  13. Winebarger Paul M. (Austin TX) Zaleski Mark A. (Austin TX) Morrison Troy B. (Austin TX) Sultemeier Jeffrey J. (Buda TX), Selective cleaning process for fabricating a semiconductor device.
  14. Tobben Dirk,DEX ; Gambino Jeffrey, Self-aligned metal caps for interlevel metal connections.
  15. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
  16. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
  17. Grebinski Thomas J. (Sunnyvale CA), Surface treatment to remove impurities in microrecesses.
  18. Akram Salman ; Meikle Scott G., Tantalum-aluminum-nitrogen material for semiconductor devices.
  19. Berman Michael J. ; Kalpathy-Cramer Jayashree, Use of ethylene glycol as a corrosion inhibitor during cleaning after metal chemical mechanical polishing.

이 특허를 인용한 특허 (32)

  1. Kawanami, Koji; Tabuchi, Kiyotaka, Method for production of semiconductor devices.
  2. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  3. Gonohe, Narishi; Harada, Masamichi; Kato, Nobuyuki, Selective W-CVD method and method for forming multi-layered Cu electrical interconnection.
  4. Usami,Tatsuya, Semiconductor device and manufacturing method thereof.
  5. Usami,Tatsuya, Semiconductor device and manufacturing method thereof.
  6. Lin, Chun-Chieh; Su, Hung-Wen; Tsai, Ming-Hsing; Jang, Syun-Ming, Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components.
  7. Minamihaba,Gaku; Yano,Hiroyuki; Kurashima,Nobuyuki; Yamamoto,Susumu, Semiconductor device including a discontinuous film and method for manufacturing the same.
  8. Kojima,Hideyuki, Semiconductor device with suppressed copper migration.
  9. Kim, Ho-Jun; Lee, Hae-Wang; Park, Chul-Hong; Sohn, Dong-Kyun; Yoon, Jong-Shik, Semiconductor devices having contacts with intervening spacers and method for fabricating the same.
  10. Saito, Tatsuyuki; Ohashi, Naohumi; Imai, Toshinori; Noguchi, Junji; Tamaru, Tsuyoshi, Semiconductor integrated circuit device and a method of manufacturing the same.
  11. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  12. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  13. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  14. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  15. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  16. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  17. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  20. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  21. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  22. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  23. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  24. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  25. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  26. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  27. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  28. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  29. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  30. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  31. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  32. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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