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Self-synchronous logic circuit having test function and method of testing self-synchronous logic circuit

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/00
  • G01R-031/28
  • G06F-011/22
출원번호 US-0448076 (2003-05-30)
우선권정보 JP-0157567 (2002-05-30)
발명자 / 주소
  • Yamanaka, Hidekazu
  • Horiyama, Takashi
출원인 / 주소
  • Sharp Kabushiki Kaisha
대리인 / 주소
    Harness, Dickey & Pierce, P.L.C.
인용정보 피인용 횟수 : 52  인용 특허 : 3

초록

A self-synchronous logic circuit includes scan test compliant registers holding data and forming stages of a pipeline, and scan test compliant self-synchronous signal control circuits corresponding to respective registers and performing handshake to transfer clocks. In accordance with the clocks tra

대표청구항

1. A self-synchronous logic circuit having a test function, comprising:registers holding data, connected in a plurality of stages for a pipeline; andself-synchronous signal control circuits provided corresponding to said registers connected in a plurality of stages, respectively; whereinsaid self-sy

이 특허에 인용된 특허 (3)

  1. Ivan E. Sutherland ; Scott M. Fairbanks ; Josephus C. Ebergen, Asynchronously controlling data transfers within a circuit.
  2. Singh, Montek; Nowick, Steven M., High-throughput asynchronous dynamic pipelines.
  3. Fujii Koji,JPX ; Douseki Takakuni,JPX, Self-timed pipelined datapath system and asynchronous signal control circuit.

이 특허를 인용한 특허 (52)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  16. Ramchandran,Amit, Cache for instruction set architecture using indexes to achieve compression.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  20. Franko,Jaemon D., Detection of tap register characteristics.
  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  22. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  24. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  25. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  26. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Ramchandran,Amit, Input pipeline registers for a node in an adaptive computing engine.
  31. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  32. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  33. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  34. Parulkar, Ishwardutt; Ebergen, Josephus C.; Elkin, Ilyas, Method and apparatus for test of asynchronous pipelines.
  35. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  36. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  41. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  44. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  45. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  46. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  47. Chester, David B., Propagating reconfiguration command over asynchronous self-synchronous global and inter-cluster local buses coupling wrappers of clusters of processing module matrix.
  48. Muramatsu,Tsuyoshi; Yamanaka,Hidekazu; Tokura,Atsushi; Urata,Takuji, Self-synchronous FIFO memory device.
  49. Master,Paul L.; Watson,John, Storage and delivery of device features.
  50. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  51. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  52. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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