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Fault-tolerant computer system with voter delay buffer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0548528 (2000-04-13)
발명자 / 주소
  • Somers, Jeffrey S.
  • Huang, Wen-Yi
  • Tetreault, Mark D.
  • Wegner, Timothy M.
출원인 / 주소
  • Stratus Technologies Bermuda, Ltd.
대리인 / 주소
    Testa, Hurwitz & Thibeault, LLP
인용정보 피인용 횟수 : 13  인용 특허 : 209

초록

A fault-tolerant computer system includes first and second central processing units (CPUs) producing essentially identical data output streams, a voter delay buffer having a first FIFO buffer and a second FIFO buffer, and an I/O module connected to the CPUs. The I/O module includes a comparator for

대표청구항

1. A fault-tolerant computer system suitable for exchanging data with peripheral devices, said computer system comprising:a first central processing unit (CPU) having at least one first CPU buffer,a second CPU having at least one second CPU buffer, said second CPU being operationally coupled to said

이 특허에 인용된 특허 (209)

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  6. Safford,Kevin David; Lyles,Christopher L.; Delano,Eric Richard, Core-level processor lockstepping.
  7. Gibart,Anthony Gerard; Kucharski,Paul G.; Izzo,Joseph Paul; Kalan,Michael Dean; Rischar,Charles Martin, High speed synchronization in dual-processor safety controller.
  8. Safford,Kevin David; Delano,Eric Richard, Lockstep error signaling.
  9. Safford,Kevin David; Soltis, Jr.,Donald Charles; Delano,Eric Richard, Off-chip lockstep checking.
  10. Chenu, Eric, Secure checking of the exclusivity of an active/passive state of processing units.
  11. Yamada, Hiromichi; Kanekawa, Nobuyasu; Sakata, Teruaki; Hagiwara, Kesami; Ishiguro, Yuichi, Semiconductor integrated circuit and method for operating same.
  12. Lupescu, Grigore G., System and method for error detection in a critical system.
  13. Fiorentino, Richard D.; Kaman, Charles H.; Troiani, Mario; Muench, Erik, System for cross-host, multi-thread session alignment.
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