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Field effect transistor and method of fabrication 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-031/072
출원번호 US-0306640 (2002-11-27)
발명자 / 주소
  • Chau, Robert S.
  • Barlage, Doulgas
  • Jin, Been-Yih
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 52  인용 특허 : 11

초록

The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pa

대표청구항

1. A transistor comprising:a channel region formed from a narrow bandgap semiconductor film formed on insulating substrate;a gate dielectric formed on said narrow bandgap semiconductor film;a gate electrode formed on said gate dielectric; anda pair of source/drain regions formed from a semiconductor

이 특허에 인용된 특허 (11)

  1. Kiely Philip A. (Tinton Falls NJ) Taylor Geoffrey W. (Holmdel NJ), Buried channel heterojunction field effect transistor.
  2. Boos John Bradley ; Kruppa Walter ; Park Doewon ; Bennett Brian R., Electronic devices with InAlAsSb/AlSb barrier.
  3. Candelaria Jon J. (Tempe AZ), Enhanced mobility MOSFET device and method.
  4. Currie John F.,CAX ; Sundararaman Chetlur S.,CAX, Field effect devices.
  5. Shibasaki Ichiro (Fuji JPX) Nagase Kazuhiro (Fuji JPX), Field effect transistor.
  6. Takemura Yasuhiko (Kanagawa JPX), Gate insulated semiconductor device.
  7. Yoshimi Makoto (Tokyo JPX) Inaba Satoshi (Tokyo JPX) Murakoshi Atsushi (Tokyo JPX) Terauchi Mamoru (Tokyo JPX) Shigyo Naoyuki (Tokyo JPX) Matsushita Yoshiaki (Tokyo JPX) Aoki Masami (Tokyo JPX) Hamam, Insulated-gate transistor having narrow-bandgap-source.
  8. Thornton Robert L. (Palo Alto CA), Lateral heterojunction bipolar transistor (LHBT) and suitability thereof as a hetero transverse junction (HTJ) laser.
  9. Eimori Takahisa (Hyogo JPX), Semiconductor device and manufacturing method thereof.
  10. Mitsui Katsuyoshi (Hyogo JPX) Shimizu Masahiro (Hyogo JPX), Semiconductor device including a field effect transistor.
  11. Augusto Carlos Jorge Ramiro Proenca,BEX, Vertical MISFET devices.

이 특허를 인용한 특허 (52)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  4. Pillarisetty, Ravi; Hudait, Mantu K.; Radosavljevic, Marko; Dewey, Gilbert; Rakshit, Titash; Kavalieros, Jack T., Double quantum well structures for transistors.
  5. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  6. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Pillarisetty, Ravi; Jin, Been-Yih; Rachmady, Willy; Radosavljevic, Marko, Germanium on insulator (GOI) semiconductor substrates.
  16. Radosavljevic, Marko; Chu-Kung, Benjamin; Dewey, Gilbert; Mukherjee, Niloy, Increasing carrier injection velocity for integrated circuit devices.
  17. Radosavljevic, Marko; Chu-Kung, Benjamin; Dewey, Gilbert; Mukherjee, Niloy, Increasing carrier injection velocity for integrated circuit devices.
  18. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  19. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  20. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  21. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  22. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  23. Lee, Jongwon; Yoon, Boun; Han, Sang Yeob; Kim, Chae Lyoung, Methods of forming CMOS transistors with high conductivity gate electrodes.
  24. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  25. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  26. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  27. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  28. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  29. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  30. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  31. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  32. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  33. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  34. Pillarisetty, Ravi; Shah, Uday; Rakshit, Titash; Kavalieros, Jack T.; Doyle, Brian S., Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin.
  35. Pillarisetty, Ravi; Shah, Uday; Doyle, Brian S.; Kavalieros, Jack T., Reducing external resistance of a multi-gate device using spacer processing techniques.
  36. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  37. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  38. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  39. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  40. Pillarisetty, Ravi; Hudait, Mantu K.; Radosavljevic, Marko; Dewey, Gilbert; Rakshit, Titash; Chau, Robert S., Semiconductor heterostructures to reduce short channel effects.
  41. Liang,Yong; Li,Hao, Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures.
  42. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  43. Le, Van H.; Kennel, Harold W.; Rachmady, Willy; Pillarisetty, Ravi; Kavalieros, Jack; Mukherjee, Niloy, Strained channel region transistors employing source and drain stressors and systems including the same.
  44. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  45. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  46. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  47. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  48. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  49. Radosavljevic, Marko; Dewey, Gilbert; Mukherjee, Niloy; Pillarisetty, Ravi, Techniques and configurations to impart strain to integrated circuit devices.
  50. Kijima, Takeshi; Konishi, Akio, Transistor type ferroelectric memory and method of manufacturing the same.
  51. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  52. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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