$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Precision electroplated solder bumps and method for manufacturing thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0053159 (2002-01-15)
발명자 / 주소
  • Yap, Daniel
  • Lawyer, Philip H.
출원인 / 주소
  • HRL Laboratories, LLC.
대리인 / 주소
    Ladas & Parry
인용정보 피인용 횟수 : 32  인용 특허 : 11

초록

A solder bump structure for use on a substrate. The solder bump structure includes a multilayer underbump metallization having a major upper surface with a solder wetable caplayer for contacting a solder bump, the mutilayer underbump metallization projecting from the substrate with an exposed sidewa

대표청구항

1. A solder bump structure for use on a substrate, comprising:(a) a multilayer underbump metallization having a major upper surface with a solder wetable caplayer for contacting a solder bump, the mutilayer underbump metallization projecting from said substrate with a sidewall;(b) a layer of metal s

이 특허에 인용된 특허 (11)

  1. Carney Francis J. (Gilbert AZ) Carney George F. (Tempe AZ) Mitchell Douglas G. (Tempe AZ), Electrical interconnect and method for forming the same.
  2. Mitchell Douglas G. ; Carney Francis J. ; Woolsey Eric J., Interconnect system and method of fabrication.
  3. Kung Ling-Chen,TWX ; Hu Hsu-Tien,TWX ; Uang Ruoh-Huey,TWX ; Lu Szu-Wei,TWX ; Kuo Chun-Yi,TWX, Method for forming solder bumps of improved height and devices formed.
  4. Thomas Donald A. (Hopewell Township ; Mercer County NJ), Method for increasing the height of solder bumps.
  5. Akram Salman, Method of forming conductive bumps on die for flip chip applications.
  6. Stuart E. Greer, Method of forming copper interconnection utilizing aluminum capping film.
  7. Crafts Douglas E. (San Jose CA) Murali Venkatesan (San Jose CA) Lee Caroline S. (Fresh Meadows NY), Process for single mask C4 solder bump fabrication.
  8. Agarwala Birendra N. (Hopewell Junction NY), Process of making pad structure for solder ball limiting metallurgy having reduced edge stress.
  9. Edelstein Daniel Charles ; McGahay Vincent ; Nye ; III Henry A. ; Ottey Brian George Reid ; Price William H., Robust interconnect structure.
  10. Yung Edward K. (Carrboro NC), Solder bump fabrication method.
  11. Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd, Solder bump fabrication methods and structure including a titanium barrier layer.

이 특허를 인용한 특허 (32)

  1. Wu, Yi-Wen; Lin, Cheng-Chung; Hwang, Chien Ling; Liu, Chung-Shi, Copper pillar bump with non-metal sidewall protection structure and method of making the same.
  2. Hwang, Chien Ling; Wu, Yi-Wen; Liu, Chung-Shi, Cu pillar bump with L-shaped non-metal sidewall protection structure.
  3. Hwang, Chien Ling; Wu, Yi-Wen; Liu, Chung-Shi, Cu pillar bump with L-shaped non-metal sidewall protection structure.
  4. Hwang, Chien Ling; Wu, Yi-Wen; Wang, Chun-Chieh; Liu, Chung-Shi, Cu pillar bump with non-metal sidewall protection structure.
  5. Wu, Yi-Wen; Lin, Cheng-Chung; Hwang, Chien Ling; Liu, Chung-Shi, Cu pillar bump with non-metal sidewall protection structure.
  6. Hwang, Chien Ling; Tsai, Hui-Jung; Wu, Yi-Wen; Liu, Chung-Shi, Cu pillar bump with non-metal sidewall spacer and metal top cap.
  7. Peng, Li ping; Chou, Shen kuang Sidney; Yuen, Chi hung; Wang, Yan bin; Xiao, Lu, Magnetic head, head gimbal assembly and disk drive unit with the same, and manufacturing method thereof.
  8. Chou, Shenkuang; Peng, Liping; Wong, Kayip; Wang, Yanbin; Xiao, Lu; Zhao, Bin, Magnetic recording head, head gimbal assembly, and disk drive unit with the same.
  9. Cheng, Ming-Da; Lu, Wen-Hsiung; Lin, Chih-Wei; Chen, Ching-Wen; Wu, Yi-Wen; Chang, Chia-Tung; Ho, Ming-Che; Liu, Chung-Shi, Mechanisms for forming copper pillar bumps.
  10. Lu, Wen-Hsiung; Cheng, Ming-Da; Lin, Chih-Wei; Liu, Chung-Shi, Mechanisms for forming copper pillar bumps using patterned anodes.
  11. Lu, Wen-Hsiung; Cheng, Ming-Da; Lin, Chih-Wei; Liu, Chung-Shi, Mechanisms for forming copper pillar bumps using patterned anodes.
  12. Xiao, De Yuan; Chen, Guo Qing, Method and system for forming conductive bumping with copper interconnection.
  13. Xiao, De Yuan; Chen, Guo Qing, Method and system for forming conductive bumping with copper interconnection.
  14. Hwang, Chien Ling; Tsai, Hui-Jung; Wu, Yi-Wen; Liu, Chung-Shi, Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap.
  15. Liu, Chung-Shi; Jeng, Shin-Puu; Lii, Mirng-Ji; Yu, Chen-Hua, Method of forming electrical connections.
  16. Wu, Yi-Wen; Lin, Cheng-Chung; Hwang, Chien Ling; Liu, Chung-Shi, Method of making a conductive pillar bump with non-metal sidewall protection structure.
  17. Hwang, Chien Ling; Wu, Yi-Wen; Wang, Chun-Chieh; Liu, Chung-Shi, Method of making a pillar structure having a non-metal sidewall protection structure.
  18. Tsao,Pei Haw; Chao,Clinton; Wang,Chung Yu, Method to increase bump height and achieve robust bump structure.
  19. Farnworth, Warren M.; Lake, Rickie C.; Hiatt, William M., Microfeature workpieces having alloyed conductive structures, and associated methods.
  20. Tsai, Tsung-Fu; Zhan, Chau-Jie; Chang, Jing-Yao; Chang, Tao-Chih, Package carrier.
  21. Liu, Chung-Shi; Yu, Chen-Hua, Self-aligned protection layer for copper post structure.
  22. Liu, Chung-Shi; Yu, Chen-Hua, Self-aligned protection layer for copper post structure.
  23. Liu, Chung-Shi; Yu, Chen-Hua, Self-aligned protection layer for copper post structure.
  24. Liu, Chung-Shi; Yu, Chen-Hua, Self-aligned protection layer for copper post structure.
  25. Lai, Yi-Jen; Han, Chih-Kang; Chan, Chien-Pin; Chien, Chih-Yuan; Yang, Huai-Tei, Semiconductor device and semiconductor assembly with lead-free solder.
  26. Lai, Yi-Jen; Han, Chih-Kang; Chan, Chien-Pin; Chien, Chih-Yuan; Yang, Huai-Tei, Semiconductor device and semiconductor assembly with lead-free solder.
  27. Wada, Tamaki; Tobita, Akihiro; Ichihara, Seiichi, Semiconductor device having electrode/film opening edge spacing smaller than bonding pad/electrode edge spacing.
  28. Seo, Sun-kyoung; Ryu, Seung-kwan; Choi, Ju-il; Cho, Tae-je; Kwon, Yong-hwan, Semiconductor devices with solder-based connection terminals and method of forming the same.
  29. Coolbaugh, Douglas D.; Edelstein, Daniel C.; Eshun, Ebenezer E.; He, Zhong-Xiang; Rassel, Robert M.; Stamper, Anthony K., Terminal pad structures and methods of fabricating same.
  30. Coolbaugh,Douglas D.; Edelstein,Daniel C.; Eshun,Ebenezer E.; He,Zhong Xiang; Rassel,Robert M.; Stamper,Anthony K., Terminal pad structures and methods of fabricating same.
  31. Coolbaugh,Douglas D.; Edelstein,Daniel C.; Eshun,Ebenezer E.; He,Zhong Xiang; Rassel,Robert M.; Stamper,Anthony K., Terminal pad structures and methods of fabricating same.
  32. Hammedinger, Robert; Kastner, Konrad; Maier, Martin; Obesser, Michael, Weldable contact and method for the production thereof.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로