[특허]Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer

Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/52
출원번호	US-0112833 (2002-03-29)
발명자 / 주소	Koutny, Jr., William W. C.
출원인 / 주소	Silicon Magnetic Systems
대리인 / 주소	Daffer Kevin L.
인용정보	피인용 횟수 : 6 인용 특허 : 113

초록 ▼

A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, the method may form a surface in which an upper surface of the fill layer is substantially level with at least one of the peaks associated with the surface roughness of the metal layer. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In other cases, the method may include forming a surface in which the fill layer is arranged above the metal layer-fill layer interface. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained.

대표청구항 ▼

1. A magnetic random access memory device comprising an upper layer arranged upon a lower layer, wherein the lower layer comprises:a metal surface having a plurality of peaks and valleys associated with the roughness of the metal surface; anda fill material arranged within the valleys, wherein an upper surface of said fill material is substantially level with at least one of said peaks. 2. The magnetic random access memory device of claim 1, wherein said fill material comprises a dielectric. 3. The magnetic random access memory device of claim 1, wherein said fill material comprises a conductive material. 4. The magnetic random access memory device of claim 1, wherein said metal surface comprises aluminum. 5. The magnetic random access memory device of claim 1, wherein the lower layer comprises a digit line of the magnetic random access memory device. 6. A semiconductor structure, comprising:an interface comprising laterally adjacent portions of a metal layer and a fill layer, wherein an upper boundary of said interface is denoted by an upper most portion of said metal layer and laterally adjacent portions of said fill layer, and wherein a lower boundary of said interface is denoted by a lower most portion of said fill layer and laterally adjacent portions of said metal layer; andan additional portion of the fill layer formed above the upper lateral boundary having a thickness less than a thickness of the interface. 7. The semiconductor structure of claim 6, wherein the thickness of the interface is at least approximately 70 angstroms. 8. The semiconductor structure of claim 6, wherein the thickness of the additional portion of the fill layer is less than approximately 40 angstroms. 9. The semiconductor structure of claim 6, further comprising one or more metal surfaces adapted for electrical connection with a conductive layer. 10. The semiconductor structure of claim 9, wherein said one or more metal surfaces is the lowermost surface of the semiconductor structure or one or more sidewalls of the semiconductor structure. 11. The magnetic random access memory device of claim 1, wherein the lower layer comprises a mean surface roughness less than approximately 80 angstroms. 12. The magnetic random access memory device of claim 11, wherein the first layer comprises a mean surface roughness less than approximately 10 angstroms. 13. The magnetic random access memory device of claim 11, wherein the first layer comprises a mean surface roughness between approximately 2 angstroms and approximately 4 angstroms. 14. The magnetic random access memory device of claim 3, wherein the fill layer comprises a different material than the metal surface. 15. The magnetic random access memory device of claim 3, wherein the fill layer comprises the same material as the metal surface. 16. The magnetic random access memory device of claim 1, wherein the fill material comprises different polish characteristics than the metal surface. 17. The magnetic random access memory device of claim 1, wherein the fill material comprises a metal nitride. 18. The magnetic random access memory device of claim 1, wherein the fill material comprises a metal oxide. 19. The semiconductor structure of claim 8, wherein the thickness of the additional portion of the fill layer is between approximately 15 angstroms and approximately 40 angstroms.

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Barry John L. (North St. Paul MN) Bell Donald R. (White Bear Township ; Ramsey County MN) Chesley Jason A. (Hudson WI) Rude Harold E. (Roseville MN) Sheffield William F. (Oakdale MN) Slama David F. (, Abrading apparatus.
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Nelson Leonard E. (Lake Elmo MN) Van Loc X. (Minneapolis MN), Abrasive composition and articles incorporating same.
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Waldo Whitson G. (Chandler AZ) Genduso Lawrence M. (Chandler AZ), Alignment reticle for a semiconductor wafer stepper system and method of use.
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Southwick Scott A., Apparatus and method for refurbishing fixed-abrasive polishing pads used in chemical-mechanical planarization of semicon.
상세보기
Schultz Laurence D. (Boise ID) Tuttle Mark E. (Boise ID) Doan Trung T. (Boise ID), Apparatus for planarizing semiconductor wafers, and a polishing pad for a planarization apparatus.
상세보기
Doy Toshiroh K. (Tokorozawa JPX) Nakada Hiroshi (Tokyo JPX) Kunimitsu Yoshihiko (Shinnanyo JPX), Apparatus for polishing.
상세보기
Ho Herbert (Washingtonville NY) Hammerl Erwin (Stormville NY) Dobuzinsky David M. (Hopewell Junction NY) Palm J. Herbert (Wappingers Falls NY) Fugardi Stephen (New Milford CT) Ajmera Atul (Wappinger , Application of thin crystalline Si₃N₄liners in shallow trench isolation (STI) structures.
상세보기

Beyer Klaus D. (Poughkeepsie NY) Guthrie William L. (Poughkeepsie NY) Makarewicz Stanley R. (New Windsor NY) Mendel Eric (Poughkeepsie NY) Patrick William J. (Newburgh NY) Perry Kathleen A. (Lagrange, Chem-mech polishing method for producing coplanar metal/insulator films on a substrate.
상세보기

Cooperman Steven S. (Southborough MA) Nasr Andre I. (Marlborough MA), Chemical mechanical planarization of shallow trenches in semiconductor substrates.
상세보기

Schonauer Diana M. (San Jose CA) Avanzino Steven C. (Cupertino CA), Chemical solutions for removing metal-compound contaminants from wafers after CMP and the method of wafer cleaning.
상세보기

Caldwell Roger F. (Milpitas CA), Chemical-mechanical alignment mark and method of fabrication.
상세보기

Shimomura Mariko (Yokohama JPX) Miyashita Naoto (Yokohama JPX) Ohashi Hiroyuki (Kamakura JPX), Chemical-mechanical polishing (CMP) method for controlling polishing rate using ionized water, and CMP apparatus.
상세보기

Salugsugan Isidore (Fremont CA), Chemical-mechanical polishing of thin materials using a pulse polishing technique.
상세보기

Doan Trung T. (Boise ID) Meikle Scott (Boise ID), Chemical-mechanical polishing processes of planarizing insulating layers.
상세보기

Yu Chris C. (Irvine CA) Yu Tat-Kwan (Austin TX), Chemical-mechanical-polishing pad cleaning process for use during the fabrication of semiconductor devices.
상세보기

Brunner Roland (Reut DEX) Hochgesang Georg (Burghausen DEX) Schnegg Anton (Burghausen DEX) Thalhammer Gertraud (Burghausen DEX), Cleaning agent and method for cleaning semiconductor wafers.
상세보기

Eisenberg Juli H. (Allentown PA) Fritzinger Larry B. (Bethlehem PA) Fu Chong-Cheng (South Whitehall PA) Kook Taeho (Lower Macungie Township ; Lehigh County PA) Wolf Thomas M. (Laurys Station PA), Compensation of lithographic and etch proximity effects.
상세보기

Gill ; Jr. Gerald L. (3502 E. Atlanta Ave. Phoenix AZ 85040), Counterbalanced polishing apparatus.
상세보기

Jain Manoj K. (Plano TX), Damascene conductors with embedded pillars.
상세보기

Huckels Kai ; Ilg Matthias, Dishing resistance.
상세보기

Harvey Jerry L., Dummy fill patterns to improve interconnect planarity.
상세보기

Jaso Mark A. ; Schnabel Rainer F., Dummy patterns for aluminum chemical polishing (CMP).
상세보기

Sethuraman Anantha R. ; Koutny ; Jr. William W. C., Employing an acidic liquid and an abrasive surface to polish a semiconductor topography.
상세보기

Koutny ; Jr. William W. C., Employing deionized water and an abrasive surface to polish a semiconductor topography.
상세보기

Cronin John E. (Milton VT) Morrett Kent E. (Essex Junction VT) Potter Michael D. (Grand Isle VT) Rutten Matthew J. (Milton VT), Fabrication methods for bidirectional field emission devices and storage structures.
상세보기

Ottman John C. (San Jose CA) Shen John C. S. (Rochester MN), Fixed abrasive polishing method and apparatus.
상세보기

Walker Michael A. ; Robinson Karl M., Fixed abrasive polishing pad.
상세보기

Highberg Carle W. (Sylvania OH), Fixed-super-abrasive tool and method of manufacture thereof.
상세보기

Karlsson Olov B. ; Lyons Christopher F. ; Van Ngo Minh ; Bell Scott A. ; Foote David K., Gate pattern formation using a bottom anti-reflective coating.
상세보기

Gabor Thomas (Maplewood MN) Broberg David E. (Woodbury MN) Dierssen Gunther H. (White Bear Lake MN) Rowenhorst Donley D. (North St. Paul MN), Granular silicon carbide abrasive grain coated with refractory material, method of making the same and articles made the.
상세보기

Fisher Wayne G. (Allen TX), Integrated circuit planarization by mechanical polishing.
상세보기

Yamada Yuichi (Kawasaki JPX) Ayata Naoki (Machida JPX) Suzukawa Hiroki (Yokohama JPX) Nogawa Hideki (Tokyo JPX), Mark detecting method and apparatus.
상세보기

Jain Manoj K. (Plano TX), Mechanical scrubbing for particle removal.
상세보기

Imaizumi Masaaki (Tokyo JPX) Nishimori Eiji (Tokyo JPX) Ichida Yasuteru (Machida JPX) Ayata Naoki (Machida JPX), Method and apparatus for detecting position of a mark.
상세보기

Hudson Guy F., Method for chemical-mechanical planarization of a substrate on a fixed-abrasive polishing pad.
상세보기

Sethuraman Anantha R. ; Koutny ; Jr. William W. C., Method for cleaning a surface of a dielectric material.
상세보기

Mikagi Kaoru (Tokyo JPX), Method for fabricating semiconductor device with interconnections buried in trenches.
상세보기

Fiordalice Robert W. (Austin TX) Maniar Papu D. (Austin TX) Klein Jeffrey L. (Austin TX), Method for forming inlaid interconnects in a semiconductor device.
상세보기

Wang Jyh-Lih,TWX ; Chen Yung-Shun,TWX, Method for improving the planarity of shallow trench isolation.
상세보기

Poon Stephen S. (Austin TX) Gelatos Avgerinos V. (Austin TX), Method for polish planarizing a semiconductor substrate by using a boron nitride polish stop.
상세보기

Fusco Albert J. (East Boston MA) Cochran Bruce C. (Lexington MA), Method for polishing detector material.
상세보기

Nakajima Tsutomu,JPX ; Hayashi Yoshihiro,JPX, Method for polishing semiconductor substrate and apparatus for the same.
상세보기

Meister Thomas (Taufkirchen DEX) Stengl Reinhard (Stadtbergen DEX), Method for producing a semiconductor layer structure having a planarized surface and the use thereof in the manufacture.
상세보기

Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
상세보기

Maniar Papu D. (Austin TX) Fiordalice Robert W. (Austin TX), Method for providing trench isolation and borderless contact.
상세보기

Wells Raymond C. (Scottsdale AZ), Method for single sided polishing of a semiconductor wafer.
상세보기

Aitken John M. (Mahopac NY) Akbar Shahzad (Austin TX) Crowder Billy L. (Putnam Valley NY) Iqbal Asif (Danbury CT) Nihal Perwaiz (Hopewell Junction NY), Method of Fabricating a micro-coaxial wiring structure.
상세보기

Yu Chris C. (Boise ID) Doan Trung T. (Boise ID) Laulusa Alan E. (Boise ID), Method of chemical mechanical polishing aluminum containing metal layers and slurry for chemical mechanical polishing.
상세보기

Gambino Jeffrey P. (Gaylordsville CT) Jaso Mark A. (Yorktown Heights NY) Nesbit Larry A. (Wallingford CT), Method of chemically mechanically polishing an electronic component.
상세보기

Yamada Yuichi (Kawasaki JPX) Ayata Naoki (Machida JPX) Suzukawa Hiroki (Yokohama JPX) Nogawa Hideki (Ohizumimachi JPX), Method of detecting position of a mark.
상세보기

Tseng Horng-Huei,TWX, Method of eliminating dishing effect in polishing of dielectric film.
상세보기

Lin Benjamin Szu-Min,TWX ; Chao Fang-Ching,TWX, Method of fabricating a dual damascene structure.
상세보기

Jang Syun-Ming,TWX ; Chen Ying-Ho,TWX ; Chang Chung-Long,TWX ; Yu Chen-Hua,TWX, Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing.
상세보기

Tasaka Kazuhiro (Tokyo JPX), Method of fabricating an BPSG-filled trend and oxidation isolation structure with a gate electrode.
상세보기

Caldwell Roger F. (Milpitas CA), Method of fabrication an inverse open frame alignment mark.
상세보기

Wang Larry Yu, Method of forming a zero layer mark for alignment in integrated circuit manufacturing process employing shallow trench i.
상세보기

Prigge Helene (Unterschleissheim DEX) Schnegg Anton (Burghausen DEX) Brehm Gerhard (Emmerting DEX) Jacob Herbert (Burghausen DEX), Method of haze-free polishing for semiconductor wafers.
상세보기

Boyd John M. (Woodlawn CAX) Ellul Joseph P. (Nepean CAX) Tay Sing P. (Nepean CAX), Method of making integrated circuits.
상세보기

Sakao Masato (Tokyo JPX), Method of manufacturing semiconductor device using chemical-mechanical polishing.
상세보기

Jang Syun-Ming,TWX ; Chen Ying-Ho,TWX ; Chang Jui-Yu,TWX ; Yu Chen-Hua,TWX, Method of photo alignment for shallow trench isolation chemical-mechanical polishing.
상세보기

Yu Chris C. (Austin TX), Method of polishing a semiconductor substrate.
상세보기

Muroyama Masakazu,JPX, Method of polishing a semiconductor substrate during production of a semiconductor device.
상세보기

Banks Edward L. (Willingboro NJ), Method of polishing a semiconductor wafer.
상세보기

Tsu Shih TW; Ying-Ho Chen TW; Jih-Churng Twu TW, Method to prevent copper CMP dishing.
상세보기

Banks Edward L. (Willingboro Township ; Burlington County NJ), Methods and apparatus for polishing a semiconductor wafer.
상세보기

Eric Ian Hanson, Methods for improved planarization post CMP processing.
상세보기

Rostoker Michael D. (San Jose CA) Pasch Nicholas F. (Pacifica CA), Methods of cleaning semiconductor substrates after polishing.
상세보기

Subramanian Chitra K. (Austin TX) Perera Asanga H. (Austin TX) Hayden James D. (Austin TX) Iyer Subramoney V. (Austin TX), Multi-step planarization process using polishing at two different pad pressures.
상세보기

Larson Eric G. (Lake Elmo MN) Sanders ; Jr. Rufus C. (Burnsville MN) Niccum Brent D. (North St. Paul MN) Pawlikowski Walter W. (St. Paul MN) Edblom Elizabeth C. (Minneapolis MN), Nonwoven abrasive article and method of making same.
상세보기

Muller Karl Paul ; Poschenrieder Bernhard,FRX ; Roithner Klaus, Pad stack with a poly SI etch stop for TEOS mask removal with RIE.
상세보기

Hwang Joon (Jincheonkun KRX) Lee Hyun G. (Seongbukku KRX) Kim Hong L. (Seongnamsi KRX) Yi Young B. (Seochoku KRX) In Jae S. (Suwonsi KRX), Photomask having alignment marks.
상세보기

Nasr Andre I. (Marlborough MA) Cooperman Steven S. (Southborough MA), Planarization process for IC trench isolation using oxidized polysilicon filler.
상세보기

Sethuraman Anantha R. ; Seams Christopher A., Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect.
상세보기

Cronin John E. (Milton VT) Landis Howard S. (Underhill VT), Planarized semiconductor structure using subminimum features.
상세보기

Gill ; Jr. Gerald L. (Scottsdale AZ) Rioux Philip J. (Glendale AZ), Polishing apparatus.
상세보기

Takiyama Masahiro (Shiojiri JPX) Miyazaki Kunihiro (Shiojiri JPX) Shiozawa Kenichiro (Ashiya JPX), Polishing pad for semiconductor wafers.
상세보기

McConnell Christopher F. (Gulph Mills PA) Walter Alan E. (Exton PA), Process and apparatus for treating wafers with process fluids.
상세보기

Walsh Robert J. (Ballwin MO), Process for chemical-mechanical polishing of III-V semiconductor materials.
상세보기

Venkatesan Suresh (Austin TX) Poon Stephen (Austin TX), Process for fabricating a semiconductor device using dual planarization layers.
상세보기

Malazgirt Alp (Fremont CA) Padmakumar Bala (Sunnyvale CA) Bhattacherjee Arya (Fremont CA), Process for improved planarization of the passivation layers for semiconductor devices.
상세보기

O\Connor Loretta J. (Westford VT) Previti-Kelly Rosemary A. (Richmond VT) Reen Thomas J. (Essex Junction VT), Process for metallized vias in polyimide.
상세보기

Nagashima Naoki (Kanagawa JPX) Takahashi Hiroshi (Kanagawa JPX), Process for planarizing surface of a semiconductor device.
상세보기

Smith ; Jr. William Charles (Verbank NY) Lord Donn Allan (Hyde Park NY), Programmable apparatus for cleaning semiconductor elements.
상세보기

Sun Shih-Wei (Austin TX), Protection device for an intergrated circuit and method of formation.
상세보기

Fleming ; Jr. Marshall J. (Underhill VT) Syverson William A. (Colchester VT) White Eric J. (Essex Junction VT), Reduction of foreign particulate matter on semiconductor wafers.
상세보기

Cote William J. (Poughquag NY) Lee Pei-Ing P. (Williston VT) Sandwick Thomas E. (Hopewell Junction NY) Vollmer Bernd M. (Wappingers Falls NY) Vynorius Victor (Pleasant Valley NY) Wolff Stuart H. (Tul, Refractory metal capped low resistivity metal conductor lines and vias.
상세보기

Muroyama Masakazu (Kanagawa JPX) Sato Junichi (Tokyo JPX), Refractory metal plug forming method.
상세보기

Blackwell, Robert E., Removing slurry residue from semiconductor wafer planarization.
상세보기

Chappell Barbara A. (Amawalk NY) Davari Bijan (Mahopac NY) Sai-Halasz George A. (Mt. Kisco NY) Taur Yuan (Bedford NY), SRAM cell with capacitor.
상세보기

Hsu, David S. Y., Selective area platinum film deposition.
상세보기

Landers William Francis (Beacon NY) Rutten Matthew Jeremy (Milton VT) Fisher ; Jr. Thomas Robert (Beacon NY) Schaffer Dean Allen (South Burlington VT), Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride.
상세보기

Jang Syun-Ming,TWX ; Chen Ying-Ho,TWX ; Yu Chen-Hua,TWX, Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers.
상세보기

Hirase Junji (Osaka JPX) Hashimoto Shin (Osaka JPX), Semiconductor device and method of manufacturing the same.
상세보기

Tominaga Makoto (Tokyo JPX), Semiconductor device having an alignment mark.
상세보기

Ashigaki Shigeo,JPX ; Hamamoto Kazuhiro, Semiconductor device manufacturing method.
상세보기

Kawakubo Takashi,JPX ; Eguchi Kazuhiro,JPX ; Komatsu Shuichi,JPX ; Abe Kazuhide,JPX, Semiconductor memory device having a trench capacitor with lower electrode inside the trench.
상세보기

Olesen Michael B. (Yorba Linda CA) Bran Mario E. (Garden Grove CA), Semiconductor wafer cleaning system.
상세보기

Jang Syun-Ming (Hsin-Chu TWX) Chen Ying-Ho (Taipei TWX) Yu Chen-Hua (Hsin-Chu TWX), Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer.
상세보기

Bose Amitava (Nashua NH) Garver Marion M. (Marlborough MA) Nasr Andre I. (Marlborough MA) Cooperman Steven S. (Southborough MA), Shallow trench isolation process for high aspect ratio trenches.
상세보기

Shepard Joseph F. (Hopewell Junction NY), Shallow trench isolation with self aligned PSG layer.
상세보기

Ajuria Sergio ; Kao Soolin, Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation.
상세보기

Cadien Kenneth C. (Portland OR) Feller Daniel A. (Portland OR), Slurries for chemical mechanical polishing.
상세보기

Adams John A. (Escondido CA) Krulik Gerald A. (San Clemente CA) Harwood C. Randall (Tempe AZ), Slurry recycling in CMP apparatus.
상세보기

Xi Jianping (Golden CO) Madan Arun (Golden CO), Solar cell fabrication method.
상세보기

Cordes ; III William F. (Avon CT) Turner Edwin (Waterbury CT), Stepper process for VLSI circuit manufacture utilizing radiation absorbing dyestuff for registration of alignment marker.
상세보기

Sethuraman Anantha R. ; Koutny ; Jr. William W. C., System for cleaning a surface of a dielectric material.
상세보기

Poon Stephen S. (Austin TX) Tseng Hsing-Huang (Austin TX), Trench isolator structure in an integrated circuit.
상세보기

Pasch Nicholas F. (Pacifica CA), Trench planarization techniques.
상세보기

Shwartzman Stanley (Somerville NJ), Two step method of cleaning silicon wafers.
상세보기

Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
상세보기

Cote William J. (Essex Junction VT) Kaanta Carter W. (Colchester VT) Leach Michael A. (Winooski VT) Paulsen James K. (Jericho VT), Via-filling and planarization technique.
상세보기

Tanaka Masato (Hikone JPX) Nishizawa Hisao (Hikone JPX) Hirai Nobuyuki (Hikone JPX) Shinbara Kaoru (Hikone JPX) Yoshioka Hitoshi (Hikone JPX), Wafer cleaning method and apparatus therefore.
상세보기

Glass Thomas R., Wafer surface treatment methods and systems using electrocapillarity.
상세보기

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
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연합인증

Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer 원문보기

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연합인증

Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

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이 특허에 인용된 특허 (113)

이 특허를 인용한 특허 (6)

관련 콘텐츠

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IPC 상위 출원인

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