초록 ▼

A technique for forming a sub-0.05 μm channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the f

A technique for forming a sub-0.05 μm channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

대표청구항 ▼

1. A method of fabricating a double-gated/double channel metal oxide semiconductor field effect transistor (MOSFET) device having sub-0.05 channel lengths, said method comprising the steps of:(a) forming a patterned hard mask on a surface of a substrate, said substrate comprising at least a silicon

1. A method of fabricating a double-gated/double channel metal oxide semiconductor field effect transistor (MOSFET) device having sub-0.05 channel lengths, said method comprising the steps of:(a) forming a patterned hard mask on a surface of a substrate, said substrate comprising at least a silicon layer formed on top of an insulating region;(b) forming a patterned dummy gate stack including a polysilicon layer on a portion of said silicon layer and a portion of said patterned hard mask;(c) fanning source/drain extensions by removing said silicon layer not protected by said patterned hard mask and said patterned dummy gate stack to expose said insulating region and oxidizing exposed sidewalls of said silicon layer protected by said patterned hard mask and said patterned dummy gate stack;(d) forming an oxide layer on exposed surfaces of said insulating region and planarizing said oxide layer to expose an uppermost surface of said polysilicon layer;(e) removing said exposed polysilicon layer to provide an opening that extends to a top surface of said patterned hard mask;(f) forming a gate stack in said opening; and(g) removing said oxide layer and said patterned hard mask abutting said gate stack exposing said insulating region and portions of said silicon layer abutting said gate stack, thereby providing a double-gated/double channel MOSFET structure including said top silicon layer having a vertical thickness on the order of about 80 mn or less and vertical channel regions having a length of less than 0.05 microns located on each side of said top silicon layer, and said gate stack surrounding said vertical channel regions. 2. The method of claim 1 wherein step (a) comprises the steps of:depositing a hard mask material on said surface of said substrate; applying a photoresist to a surface of said hard mask; exposing said photoresist to a pattern of radiation; developing the pattern in said photoresist and transferring said patterned to said hard mask material via etching. 3. The method of claim 2 wherein said etching comprises reactive-ion etching. 4. The method of claim 1 wherein step (b) comprises the steps of deposition said polysilicon layer; forming a protective oxide layer on a portion of said polysilicon layer; and etching polysilicon not protected by said protective oxide layer. 5. The method of claim 1 wherein said removing step of step (c) comprises a reactive-ion etching process. 6. The method of claim 1 wherein said oxidizing step of step (c) is performed at a temperature of about 700° C. or above in an oxygen-containing atmosphere. 7. The method of claim 6 wherein said oxidizing step is performed at a temperature of from about 800° to about 900° C. 8. The method of claim 1 wherein said oxide layer employed in step (d) is comprised of TEOS that is deposited by a low-pressure chemical vapor deposition process. 9. The method of claim 1 wherein step (e) comprises a reactive-ion etching process. 10. The method of claim 1 wherein step (f) comprises forming a gate oxide in said opening on exposed sidewalls of said remaining silicon layer; filling said opening with a gate conductor; and planarizing said gate conductor. 11. The method of claim 10 wherein said gate oxide is formed by a thermal oxidation process. 12. The method of claim 10 wherein said filling step comprises deposition process selected from the group consisting of chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering, plating, evaporation, atomic layer deposition and chemical solution deposition. 13. The method of claim 10 wherein said gate conductor is polysilicon. 14. The method of claim 13 wherein said polysilicon is doped by ion implantation and annealing. 15. The method of claim 1 wherein step (g) comprises a wet etch process wherein HF is employed as a chemical etchant. 16. The method of claim 1 further comprising the step of forming activated diffusion regions in portions of said exposed silicon layer abutting said gate stack. 17. The method of claim 1 further comprising subjecting said gate stack to an oxidation process. 18. The method of claim 1 further comprising forming spacers on exposed sidewalls of said gate stack. 19. The method of claim 16 further comprising saliciding said diffusion regions.