초록 ▼

Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation l

Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

대표청구항 ▼

1. A method of forming a semiconductor device, the method comprising:providing a semiconductor substrate; forming a first dielectric layer; patterning the first dielectric layer to form a first opening; forming a conductive region in the first opening; and electrolessly plating a passivation layer o

1. A method of forming a semiconductor device, the method comprising:providing a semiconductor substrate; forming a first dielectric layer; patterning the first dielectric layer to form a first opening; forming a conductive region in the first opening; and electrolessly plating a passivation layer over the conductive region. 2. The method of claim 1 further comprising forming a second dielectric layer over the passivation layer and forming a void in the second dielectric layer.3. The method of claim 2, wherein the conductive region comprises copper and the passivation layer comprises an element selected from the group consisting of copper, nickel, phosphorus, tungsten, and rhenium.4. The method of claim 3, wherein the passivation layer comprises a material selected from the group consisting of CoWP, CoP, NiWP, NiB, CoWB, NiReP, and CoReP.5. The method of claim 1 wherein electrolessly plating the passivation layer further comprises placing the semiconductor substrate in an electrolyte comprising metal ions and a reducing agent.6. The method of claim 1 wherein electrolessly plating comprises:etching the conductive region to recess the conductive region; spraying a catalyst solution to catalytically activate the conductive region; spraying a chelating solution to remove excess of the catalyst solution; and cleaning the surface of the passivation layer to remove residual ions and defects. 7. The method of claim 5 wherein etching the conductive region further comprises removing oxides from the surface of the conductive region.8. A method of forming a semiconductor device, the method comprising:providing a semiconductor substrate; forming a first dielectric layer; patterning the first dielectric layer to form a first opening and a second opening, wherein the first opening and the second opening are adjacent each other and separated from each other; forming a first current carrying region in the first opening; forming a second current carrying region in the second opening; plating a second conductive layer over the first opening and the second opening to form a first cap and a second cap, wherein the first cap and the second cap are physically isolated from each other. 9. The method of claim 8, wherein plating the second conductive layer over the first opening to form the first cap, further comprises plating the second conductive layer over a portion of the first dielectric layer.10. The method of claim 9, wherein plating the second conductive layer further comprises plating the second conductive layer over a portion of the first dielectric layer.11. The method of claim 8 further comprising forming a dielectric layer over the first cap and the second cap and forming a void in the second dielectric layer.12. The method of claim 8, wherein the first current carrying region and the second current carrying region comprise copper and the first cap and the second cap comprise an element selected from the group consisting of copper, nickel, phosphorus, tungsten, and rhenium.13. The method of claim 12, wherein the first cap and the second cap comprise a material selected from the group consisting of CoWP, CoP, NiWP, NiB, CoWB, NiReP, and CoReP.14. The method of claim 8 wherein plating the first cap further comprises electrically plating the first cap and plating the second cap further comprises electrolessly plating the second cap.15. The method of claim 8 further comprising:etching the first and second current carrying regions to recess the first and second current carrying regions; spraying a catalyst solution to catalytically activate the first and second current carrying regions; spraying a chelating solution to remove excess of the catalyst solution; and cleaning the surfaces of the first cap to remove residual ions and defects. 16. The method of the claim 15 wherein etching the first and second current carrying regions further comprises removing oxides from the surfaces of the first current carrying region and the second current carrying region.17. A method for forming a semiconductor device, the method comprising:providing a semiconductor substrate; forming a first dielectric layer over the semiconductor substrate; forming a current carrying region within the first dielectric layer; etching the current carrying region to recess the current carrying region; providing a catalyst solution on the current carrying region to render the current carrying region catalytically active; providing a chelating solution to remove a portion of the catalyst solution; and electrolessly depositing a passivation layer over the current carrying region.