$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Insulators for high density circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023053
출원번호 US-0179110 (2002-06-24)
발명자 / 주소
  • Farrar, Paul A.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner &
인용정보 피인용 횟수 : 10  인용 특허 : 79

초록

A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foam

대표청구항

1. An integrated circuit structure comprising:a substrate; a plurality of stacked foamed polymer layers on the substrate, each of the stacked foamed polymer layers has a surface that is hydrophobic, and each of the foamed polymer layers has a cell size less than about one micron; and a plurality of

이 특허에 인용된 특허 (79)

  1. McIntosh ; III Lester H. ; Goodall Brian L. ; Shick Robert A. ; Jayaraman Saikumar, Addition polymers of polycycloolefins containing silyl functional groups.
  2. Korleski ; Jr. Joseph E., Adhesive-filler film composite.
  3. Nichols Michael F. (Columbia MO) Hahn Allen W. (Columbia MO), Article having a composite insulative coating.
  4. Susan J. Babinec ; Mechelle A. Blanchard ; Martin J. Guest ; Brian W. Walther ; Bharat I. Chaudhary ; Russell P. Barry DE, COMPOSITIONS OF INTERPOLYMERS OF .alpha.-OLEFIN MONOMERS WITH ONE OR MORE VINYL OR VINYLIDENE AROMATIC MONOMERS AND/OR ONE OR MORE HINDERED ALIPHATIC OR CYCLOALIPHATIC VINYL OR VINYLIDENE MONOMERS BL.
  5. Bertolet Allan ; Fiore James ; Gramatski Eberhard, Consolidated chip design for wire bond and flip-chip package technologies.
  6. Perelman Robert D. (Hazel Crest IL), Corrugated coaxial cable.
  7. Jang, Syun-Ming, Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material.
  8. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S., Dissolvable dielectric method.
  9. Ogitani Osamu (Koshigaya JPX) Shirose Toru (Koshigaya JPX), Electroless plating-resisting ink composition.
  10. Araps Constance J. (Wappingers Falls NY) Kandetzke Steven M. (Fishkill NY) Takacs Mark A. (Poughkeepsie NY), Electronic components comprising polyimide-filled isolation structures.
  11. Craig Jon Hawker ; James L. Hedrick ; Robert D. Miller ; Willi Volksen, Electronic devices with dielectric compositions and method for their manufacture.
  12. Matsuura Katsumi,JPX ; Takenouchi Shigeki,JPX, Electrophotographic image forming method.
  13. Kohl Paul A. ; Zhao Qiang ; Bidstrup Allen Sue Ann, Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections.
  14. Tsuruta Makoto (Tokorozawa JPX) Oda Ken (Kamihukuoka JPX), Fluororesin foam.
  15. Venkataraman Sundar Kilnagar, Foamed fluoropolymer.
  16. Topchiashvili Mikhail Izmailovich (ULITSA Tashkentskaya ; 27/12 ; pod\ezd ; 3 Tbilisi SU) Datsko Taisia Fedorovna (PEREULOK Dekabristov ; 1 Tbilisi SU) Kikvilashvili Givi Mikhailovich (ULITSA Griboed, Foamed polymer semiconductor composition and a method of producing thereof.
  17. Muschiatti Lawrence C. (Wilmington DE), High speed insulated conductors.
  18. Matsuda Hajime,JPX, High-speed semiconductor device having a dual-layer gate structure and a fabrication process thereof.
  19. Miyamoto Hirohisa,JPX ; Hirahara Shuzo,JPX ; Shinjo Yasushi,JPX ; Tsunemi Koichi,JPX ; Saito Mitsunaga,JPX ; Hosoya Masahiro,JPX, Image forming device, image forming process, and pattern forming process, and photosensitive material used therein.
  20. Takaya Toshihiko,JPX ; Anzai Shunju,JPX ; Oikawa Tomohiro,JPX, Image-forming device and method of manufacturing dielectric sheet.
  21. Lu Jiong-Ping ; Jin Changming, Integrated circuit dielectric and method.
  22. Chiang Chien ; Fraser David B., Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics.
  23. Havemann Robert H. ; Jeng Shin-Puu ; Gnade Bruce E. ; Cho Chih-Chen, Interconnect structure with an integrated low density dielectric.
  24. Jeng Shin-Puu, Low capacitance interconnect structure for integrated circuits.
  25. Jeng Shin-Puu, Low capacitance interconnect structure for integrated circuits using decomposed polymers.
  26. Rosenmayer C. Thomas, Low dielectric constant material for use as an insulation element in an electronic device.
  27. Paul A. Farrar, Low dielectric constant shallow trench isolation.
  28. Mori Toshihiko (Kawasaki JPX), Memory device, method for reading information from the memory device, method for writing information into the memory dev.
  29. O\Connor Loretta J. (Westford VT) Previti-Kelly Rosemary A. (Richmond VT) Reen Thomas J. (Essex Junction VT), Metallized vias in polyimide.
  30. Petefish William George, Method and apparatus for improving wireability in chip modules.
  31. Farrar Paul A., Method and support structure for air bridge wiring of an integrated circuit.
  32. Chiang Chien ; Fraser David B. ; Ochoa Vicky ; Pan Chuanbin ; Tzeng Sing-Mo H., Method for forming air gaps for advanced interconnect systems.
  33. Araps Constance J. (Wappingers Falls NY) Kandetzke Steven M. (Fishkill NY) Kutner Ellen L. (Poughquag NY) Takacs Mark A. (Poughkeepsie NY), Method for preparation of semiconductor structures and devices which utilize polymeric dielectric materials.
  34. Endo Kazuhiko,JPX, Method for preparing a fluoro-containing polyimide film.
  35. Hanson David A., Method for reducing via inductance in an electronic assembly and article.
  36. Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Method of forming a semiconductor structure having an air region.
  37. Farrar Paul A., Method of forming a support structure for air bridge wiring of an integrated circuit.
  38. Gonzalez Fernando, Method of forming an isolation structure in a semiconductor device.
  39. Farrar Paul A., Method of forming foamed polymeric material for an integrated circuit.
  40. Buynoski Matthew S., Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system.
  41. Rouanet Stephane Fabrice ; McGovern William Edward ; Cao Wanqing ; Moses John M. ; Carrillo Angel L. ; Klotz Irving M., Method of forming particles using a supercritical fluid.
  42. Sachdev Krishna G. (Hopewell Junction NY) Whitaker Joel R. (Port Ewen NY) Ahmad Umar M. (Hopewell Junction NY), Method of forming patterned polyimide films.
  43. El-Kareh Badih (South Hero VT) Garnache Richard R. (Shelburne VT) Ghatalia Ashwin K. (Hopewell Junction NY), Method of making a contact to a trench isolated device.
  44. Matsuura Masazumi,JPX, Method of making a semiconductor device.
  45. Hughes Henry G. (Scottsdale AZ) Lue Ping-Chang (Scottsdale AZ) Robinson Frederick J. (Scottsdale AZ), Method of making a semiconductor device having a low permittivity dielectric.
  46. Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX) Smith Douglas M. (Albuquerque NM), Method of making a semiconductor device using a low dielectric constant material.
  47. Gardner Mark I. ; Hause Frederick N. ; May Charles E., Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication.
  48. Te Velde, Ties S., Method of manufacturing a wiring system.
  49. Fujihira Mitsuaki (Yokohama JPX), Method of manufacturing semiconductor device.
  50. Tsai Chia-Shiung,TWX ; Cheng Yao-Yi,TWX ; Tao Hun-Jan,TWX, Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material.
  51. Carey David H. (Austin TX), Methods of forming channels and vias in insulating layers.
  52. Elliott ; Jr. Jarrell R. (Northfield Center OH) Srinivasan Gokul (Akron OH) Dhanuka Manish (Akron OH) Akhaury Ranjan (Akron OH), Microcellular foams.
  53. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  54. Bhansali Ameet ; Zhu Qing, Multi-layer C4 flip-chip substrate.
  55. Tanahashi Shigeo,JPX, Multilayer circuit board.
  56. Kitamura Naoya (Yokohama JPX) Sugiyama Hisashi (Yokosuka JPX) Yamaguchi Yoshihide (Fujisawa JPX) Kyoui Masayuki (Yokohama JPX) Murooka Hideyasu (Yokohama JPX) Iwamura Ryoji (Yokohama JPX) Watanabe Ma, Multilayer wiring board fabricating method.
  57. Hung-Chang Hsieh TW, Photoresist development method employing multiple photoresist developer rinse.
  58. Jeng Shin-Puu (2508 Evergreen Dr. Plano TX 75075), Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators.
  59. Jeng Shin-Puu (Plano TX), Porous insulator for line-to-line capacitance reduction.
  60. Craig S. Allen ; Nikoi Annan ; Robert M. Blankenship ; Michael K. Gallagher ; Robert H. Gore ; Angelo A. Lamola ; Yujian You, Porous materials.
  61. Ahn Kie Y. ; Forbes Leonard, Porous silicon oxycarbide integrated circuit insulator.
  62. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
  63. Watanabe Joy Kimi ; Stankus John Joseph, Process for forming a semiconductor device.
  64. Hedrick Jeffrey Curtis ; Hedrick James Lupton ; Hilborn Jons Gunnar,CHX ; Liao Yun-Hsin ; Miller Robert Dennis ; Shih Da-Yuan, Process for making a foamed elastomeric polymer.
  65. Zaidel Simon A. (Manlius NY) Alcorn Terrence S. (Liverpool NY) Kopp William F. (Liverpool NY) Pifer George C. (North Syracuse NY), Process for making air bridges for integrated circuits.
  66. Bowman Jeffery B. (Flagstaff AZ) Hubis Daniel E. (Elkton MD) Lewis James D. (Flagstaff AZ) Newman Stephen C. (Flagstaff AZ) Staley Richard A. (Flagstaff AZ), Process for producing a high strength porous polytetrafluoroethylene product having a coarse microstructure.
  67. Gore ; Robert W., Process for producing filled porous PTFE products.
  68. Gore Robert W. (Newark DE), Process for producing porous products.
  69. White Lawrence H. (Vestal NY), Process for surface mounting flip chip carrier modules.
  70. Wojnarowski Robert J. (Ballston Lake NY) Cole Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Scotia NY) Daum Wolfgang (Schenectady NY), Processing low dielectric constant materials for high speed electronics.
  71. Wojnarowski Robert J. (Ballston Lake NY) Cole Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Scotia NY) Daum Wolfgang (Schenectady NY), Processing low dielectric constant materials for high speed electronics.
  72. Wojnarowski Robert John ; Cole Herbert Stanley ; Sitnik-Nieters Theresa Ann ; Daum Wolfgang, Processing low dielectric constant materials for high speed electronics.
  73. Hiroshi Kudo JP, Semiconductor device manufacturing method.
  74. Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Semiconductor structure having an air region and method of forming the semiconductor structure.
  75. Soo Choi Pheng,MYX ; Loh Wye Boon,MYX ; Chan Lap, Simplified dual damascene process utilizing PPMSO as an insulator layer.
  76. Paul A. Farrar, Structures and methods to enhance copper metallization.
  77. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  78. Paul A. Farrar, Three-dimensional multichip module.
  79. Gore Robert Walton (Newark DE), Very highly stretched polytetrafluoroethylene and process therefor.

이 특허를 인용한 특허 (10)

  1. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride.
  2. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride films.
  3. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride films.
  4. Goetz, Martin P.; O'Neil, Gary E., Electronic device with aerogel thermal isolation.
  5. Farrar, Paul A., Integrated circuit insulators and related methods.
  6. Farrar, Paul A., Integrated circuit insulators and related methods.
  7. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  8. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  9. Lyons, Christopher F., Polymer dielectrics for memory element array interconnect.
  10. Tang, Yu-Po; Chang, Shih-Ming; Hsieh, Ken-Hsien; Liu, Ru-Gun, Via-free interconnect structure with self-aligned metal line interconnections.

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로