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Clocked based method and devices for measuring voltage-variable capacitances and other on-chip parameters

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-03126
  • G01R-03108
  • H01L-02358
출원번호 US-0825027 (2001-04-02)
발명자 / 주소
  • Rogers, David Michael
  • Qian, Mimi Xuefeng
  • Tsao, Roger Huazne
  • Van Buskirk, Michael Allen
출원인 / 주소
  • Advanced Micro Devices, Inc.
인용정보 피인용 횟수 : 34  인용 특허 : 1

초록

A characterization method for a device under test includes applying a bias voltage to a test circuit. The test circuit includes a first transistor coupled to the device under test, a second transistor coupled to the device under test and to the first transistor. A third transistor is coupled to a du

대표청구항

1. A test circuit comprising:a first transistor pair including a first transistor and a second transistor coupled with a device under test; and a second transistor pair including a third transistor and a fourth transistor coupled with a dummy device, the first transistor and the third transistor hav

이 특허에 인용된 특허 (1)

  1. Chen-Teng Fan TW; Jyh-Herng Wang TW, Chip capacitance measurement circuit.

이 특허를 인용한 특허 (34)

  1. Doong, Yih-Yuh; Chang, Keh-Jeng; Mii, Yuh-Jier; Liu, Sally; Hung, Lien Jung; Chang, Victor Chih Yuan, Accurate capacitance measurement for ultra large scale integrated circuits.
  2. Doong, Yih-Yuh; Chang, Keh-Jeng; Mii, Yuh-Jier; Liu, Sally; Hung, Lien Jung; Chang, Victor Chih Yuan, Accurate capacitance measurement for ultra large scale integrated circuits.
  3. Doong, Yih-Yuh; Chang, Keh-Jeng; Mii, Yuh-Jier; Liu, Sally; Hung, Lien Jung; Chang, Victor Chih Yuan, Accurate capacitance measurement for ultra large scale integrated circuits.
  4. Su, Ke-Ying; Ho, Chia-Ming; Chang, Gwan Sin; Chen, Chien-Wen, Accurate parasitic capacitance extraction for ultra large scale integrated circuits.
  5. Su, Ke-Ying; Ho, Chia-Ming; Chang, Gwan Sin; Chen, Chien-Wen, Accurate parasitic capacitance extraction for ultra large scale integrated circuits.
  6. Su, Ke-Ying; Ho, Chia-Ming; Chang, Gwan-Sin; Chen, Chien-Wen, Accurate parasitic capacitance extraction for ultra large scale integrated circuits.
  7. Vollertsen, Rolf-Peter, Apparatus and method for measuring local surface temperature of semiconductor device.
  8. Carmichael, Leslie; Stein, Michele, Calculating a parasitic capacitance of an oscillator circuit.
  9. Kuang, Yu, Capacitance measurement circuit and capacitance measurement method thereof.
  10. Leroux, Charles, MOS capacitance test structure and associated method for measuring a curve of capacitance as a function of the voltage.
  11. Forbes, Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  12. Forbes, Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  13. Forbes, Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  14. Forbes,Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  15. Forbes,Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
  16. Agarwal, Kanak B.; Hayes, Jerry D.; Liu, Ying, Method and apparatus for statistical CMOS device characterization.
  17. Agarwal, Kanak B.; Hayes, Jerry D.; Liu, Ying, Method and apparatus for statistical CMOS device characterization.
  18. Acharyya, Dhruva J.; Nassif, Sani R.; Rao, Rahul M., Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks.
  19. Van der Plas, Geert; Sawada, Ken; Miyamori, Yuichi; Anchlia, Ankur; Mercha, Abdelkarim, Method and system for measuring capacitance difference between capacitive elements.
  20. Huang, Ru; Zou, Jibin; Wang, Runsheng; Fan, Jiewen; Liu, Changze; Wang, Yangyuan, Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact.
  21. Novikov, Lenny M.; Anderson, Lenworth, Micropower voltage-independent capacitance measuring method and circuit.
  22. Forbes,Leonard, NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals.
  23. Forbes,Leonard, NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals.
  24. Forbes,Leonard, NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals.
  25. Forbes,Leonard, NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals.
  26. Ma,Zhijian; Liu,Chunbo, On-chip interface trap characterization and monitoring.
  27. Joshi, Rajiv V.; Kanj, Rousaida N.; Kuang, Jente B.; Nassif, Sani R., On-chip leakage current modeling and measurement circuit.
  28. Joshi, Rajiv V.; Kanj, Rouwaida N.; Kuang, Jente B.; Nassif, Sani R., On-chip leakage current modeling and measurement circuit.
  29. Yamashita,Kyoji; Kunikiyo,Tatsuya; Watanabe,Tetsuya; Kanamoto,Toshiki, Semiconductor device.
  30. Lee, Jang Uk, Semiconductor memory device having dummy conductive patterns on interconnection and fabrication method thereof.
  31. Anderson, Brent A.; Bryant, Andres; Nowak, Edward J.; Rankin, Jed H., Spacer fill structure, method and design structure for reducing device variation.
  32. Tustaniwskyj, Jerry Ihor; Babcock, James Wittman, Temperature measurement using a diode with saturation current cancellation.
  33. Tsou, Po-Wei, Test circuit for testing a device-under-test by using a voltage-setting unit to pull an end of the device-under-test to a predetermined voltage.
  34. Kinoshita,Eita, Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit.
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