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A method for performing error correction on data read from a multistate memory array, by encoding data read from each memory element of the array, detecting an error in the encoded data from one memory element, and correcting the error by changing X bits of the encoded data (preferably X=1), and a m

A method for performing error correction on data read from a multistate memory array, by encoding data read from each memory element of the array, detecting an error in the encoded data from one memory element, and correcting the error by changing X bits of the encoded data (preferably X=1), and a multistate memory system for performing the method. Preferably the system is a circuit in which each memory element is a flash memory cell. The invention enables implementation of error detection and correction while requiring storage of fewer ECC check bits (with the data of interest) than the number of ECC check bits that would need to be stored in accordance with the prior art. In accordance with the invention, a data bit is read from each memory cell by asserting a signal having a signal value in a value range, where the value range is a member of a sequence of non-overlapping value subranges LiHi, where N is the number of states of each memory element, and N is equal to at least 3, and the value subranges are determined by values Li and Hi satisfying L1<H1<L2<H2< . . . <LN<HN. Each value subrange LiHi includes values xi, where Li<xi<Hi.

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1. A method of operating a multistate memory cell, the cell having one of 4 states, the method comprising:reading the cell to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 24 percent of X volts, or between approximately 25

1. A method of operating a multistate memory cell, the cell having one of 4 states, the method comprising:reading the cell to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 24 percent of X volts, or between approximately 25 percent and 49 percent of X volts, or between approximately 50 percent and 74 percent of X volts, or between approximately 75 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; encoding the voltage signal into one of a sequence of encoded signals E1, E2, E3, and E4, each of the encoded signals representing a unique ordered set of binary bits; and performing error detection and correction on the encoded signal to detect errors in the encoded signal and to correct correctable errors in the encoded signal. 2. The method of claim 1 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the encoded signals E1, E2, E3, and E4 represent, respectively, 00, 01, 11, and 10; reading the cell further comprises: selecting the cell from a plurality of multistate flash memory cells in an array; sensing a current in the cell indicative of the state of the cell that is represented by a charge stored on a floating gate of the cell; and converting the current into the voltage signal; encoding the voltage signal further comprises: comparing the voltage signal with a plurality of reference voltages to generate a plurality of reference signals; and converting the reference signals into the encoded signal; and performing error detection and correction comprises: decoding the encoded signal and other encoded signals to generate a field of uncorrected bits and fields of syndrome bits; decoding the syndrome bits to identify bits in the field of uncorrected bits that are in error; indicating non-correctable errors if two bits in the field of uncorrected bits are in error; generating a correction bit to correct a bit in error; and combining the field of uncorrected bits with the correction bit to generate a field of corrected bits. 3. A method of operating a multistate memory cell, the cell having one of 4 states, the method comprising:reading the cell to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 24 percent of X volts, or between approximately 25 percent and 49 percent of X volts, or between approximately 50 percent and 74 percent of X volts, or between approximately 75 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; encoding the voltage signal into one of a sequence of encoded signals E1, E2, E3, and E4, each of the encoded signals representing a unique ordered set of binary bits and adjacent ones of the encoded signals being different in only a single bit; and performing error detection and correction on the encoded signal to detect errors in the encoded signal and to correct correctable errors in the encoded signal. 4. The method of claim 3 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the encoded signals E1, E2, E3, and E4 represent, respectively, 00, 01, 11, and 10; reading the cell further comprises: selecting the cell from a plurality of multistate flash memory cells in an array; sensing a current in the cell indicative of the state of the cell that is represented by a charge stored on a floating gate of the cell; and converting the current into the voltage signal; encoding the voltage signal further comprises: comparing the voltage signal with a plurality of reference voltages to generate a plurality of reference signals; and converting the reference signals into the encoded signal; and performing error detection and correction comprises: decoding the encoded signal and other encoded signals to generate a field of uncorrected bits and fields of syndrome bits; decoding the syndrome bits to identify bits in the field of uncorrected bits that are in error; indicating non-correctable errors if two bits in the field of uncorrected bits are in error; generating a correction bit to correct a bit in error; and combining the field of uncorrected bits with the correction bit to generate a field of corrected bits. 5. A method of operating a multistate memory cell, the cell having one of 4 states, the method comprising:reading the cell to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 24 percent of X volts, or between approximately 25 percent and 49 percent of X volts, or between approximately 50 percent and 74 percent of X volts, or between approximately 75 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; converting the voltage signal into a field of bits; and performing error detection and correction on the field of bits to detect errors in the field of bits and to correct correctable errors in the field of bits. 6. The method of claim 5 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; reading the cell further comprises: selecting the cell from a plurality of multistate flash memory cells in an array; sensing a current in the cell indicative of the state of the cell that is represented by a charge stored on a floating gate of the cell; and converting the current into the voltage signal; converting the voltage signal further comprises: comparing the voltage signal with a plurality of reference voltages to generate a plurality of reference signals; and converting the reference signals into the field of bits; and performing error detection and correction comprises: decoding the field of bits and other fields of bits to generate a field of uncorrected bits and fields of syndrome bits; decoding the syndrome bits to identify bits in the field of uncorrected bits that are in error; indicating non-correctable errors if two bits in the field of uncorrected bits are in error; generating a correction bit to correct a bit in error; and combining the field of uncorrected bits with the correction bit to generate a field of corrected bits. 7. A memory system comprising:an array of memory cells wherein each of the cells has one of 4 states; a read circuit coupled to the array to read one of the cells and to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 24 percent of X volts, or between approximately 25 percent and 49 percent of X volts, or between approximately 50 percent and 74 percent of X volts, or between approximately 75 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; an encoding circuit coupled to the read circuit to encode the voltage signal into one of a sequence of encoded signals E1, E2, E3, and E4, each of the encoded signals representing a unique ordered set of binary bits; and an error detection and correction circuit coupled to the encoding circuit to detect errors in the encoded signal and to correct correctable errors in the encoded signal. 8. The memory system of claim 7 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the encoded signals E1, E2, E3, and E4, represent, respectively, 00, 01, 11, and 01; the memory system comprises an integrated circuit memory system; each of the cells comprises a multistate flash memory cell; the read circuit comprises a sense amplifier circuit to convert a current in the cell into the voltage signal; the encoding circuit comprises: three comparator circuits, each comparator circuit coupled between the sense amplifier circuit and a reference voltage to receive the voltage signal and to compare the voltage signal with the reference voltage to generate a reference signal; and a logic circuit coupled to receive the reference signals and to generate the encoded signal; the error detection and correction circuit comprises: an ECC decoder circuit coupled to the logic circuit to receive the encoded signal and other encoded signals, to assert the encoded signal representing data bits, and to generate syndrome bits from the other encoded signals representing ECC check bits; a syndrome decoder circuit coupled to receive and decode the syndrome bits, to generate correction bits based on the syndrome bits, and to assert a failure signal if the syndrome bits indicate an error in more than one of the data bits represented by the encoded signal; and a correction circuit coupled to receive the data bits represented by the encoded signal and the correction bits, to replace one of the data bits that is in error based on the correction bits, and to generate corrected bits. 9. A memory system comprising:an array of memory cells wherein each of the cells has one of 4 states; a read circuit coupled to the array to read one of the cells and to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 24 percent of X volts, or between approximately 25 percent and 49 percent of X volts, or between approximately 50 percent and 74 percent of X volts, or between approximately 75 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; an encoding circuit coupled to the read circuit to encode the voltage signal into one of a sequence of encoded signals E1, E2, E3, and E4, each of the encoded signals representing a unique ordered set of binary bits and adjacent ones of the encoded signals being different in only a single bit; and an error detection and correction circuit coupled to the encoding circuit to detect errors in the encoded signal and to correct correctable errors in the encoded signal. 10. The memory system of claim 9 therein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the encoded signals E1, E2, E3, and E4, represent, respectively, 00, 01, 11, and 01; the memory system comprises an integrated circuit memory system; each of the cells comprises a multistate flash memory cell; the read circuit comprises a sense amplifier circuit to convert a current in the cell into the voltage signal; the encoding circuit comprises: three comparator circuits, each comparator circuit coupled between the sense amplifier circuit and a reference voltage to receive the voltage signal and to compare the voltage signal with the reference voltage to generate a reference signal; and a logic circuit coupled to receive the reference signals and to generate the encoded signal; the error detection and correction circuit comprises: an ECC decoder circuit coupled to the logic circuit to receive the encoded signal and other encoded signals, to assert the encoded signal representing data bits, and to generate syndrome bits from the other encoded signals representing ECC check bits; a syndrome decoder circuit coupled to receive and decode the syndrome bits, to generate correction bits based on the syndrome bits, and to assert a failure signal if the syndrome bits indicate an error in more than one of the data bits represented by the encoded signal; and a correction circuit coupled to receive the data bits represented by the encoded signal and the correction bits, to replace one of the data bits that is in error based on the correction bits, and to generate corrected bits. 11. A memory system comprising:an array of memory cells wherein each of the cells has one of 4 states; a read circuit coupled to the array to read one of the cells and to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 24 percent of X volts, or between approximately 25 percent and 49 percent of X volts, or between approximately 50 percent and 74 percent of X volts, or between approximately 75 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; an encoding circuit coupled to the read circuit to encode the voltage signal into a field of bits; and an error detection and correction circuit coupled to the encoding circuit to detect errors in the field of bits and to correct correctable errors in the field of bits. 12. The memory system of claim 11 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the memory system comprises an integrated circuit memory system; each of the cells comprises a multistate flash memory cell; the read circuit comprises a sense amplifier circuit to convert a current in the cell into the voltage signal; the encoding circuit comprises: three comparator circuits, each comparator circuit coupled between the sense amplifier circuit and a reference voltage to receive the voltage signal and to compare the voltage signal with the reference voltage to generate a reference signal; and a logic circuit coupled to receive the reference signals and to generate the field of bits; the error detection and correction circuit comprises: an ECC decoder circuit coupled to the logic circuit to receive the field of bits and other fields of bits, to assert bits from the field of bits representing data bits, and to generate syndrome bits from bits from the other fields of bits representing ECC check bits; a syndrome decoder circuit coupled to receive and decode the syndrome bits, to generate correction bits based on the syndrome bits, and to assert a failure signal if the syndrome bits indicate an error in more than one of the bits from the field of bits representing data bits; and a correction circuit coupled to receive the bits representing data bits and the correction bits, to replace a bit that is in error based on the correction bits, and to generate corrected bits. 13. A method of operating a multistate memory cell, the cell having one of 8 states, the method comprising:reading the cell to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 12 percent of X volts, or between approximately 12.2 percent and 24 percent of X volts, or between approximately 24.2 percent and 36 percent of X volts, or between approximately 36.2 percent and 48 percent of X volts, or between approximately 48.2 percent and 60 percent of X volts, or between approximately 60.2 percent and 72 percent of X volts, or between approximately 72.2 percent and 84 percent of X volts, or between approximately 84.2 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; encoding the voltage signal into one of a sequence of encoded signals E1, E2, E3, E4, E5, E6, E7, and E8, each of the encoded signals representing a unique ordered set of binary bits; and performing error detection and correction on the encoded signal to detect errors in the encoded signal and to correct correctable errors in the encoded signal. 14. The method of claim 13 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the encoded signals E1, E2, E3, E4, E5, E6, E7, and E8 represent, respectively, 000,001, 011,010, 110, 111, 101, and 100 or 000, 100, 101, 001, 011, 111, 110, and 010; reading the cell further comprises: selecting the cell from a plurality of multistate flash memory cells in an array; sensing a current in the cell indicative of the state of the cell that is represented by a charge stored on a floating gate of the cell; and converting the current into the voltage signal; encoding the voltage signal further comprises: comparing the voltage signal with a plurality of reference voltages to generate a plurality of reference signals; and converting the reference signals into the encoded signal; and performing error detection and correction comprises: decoding the encoded signal and other encoded signals to generate a field of uncorrected bits and fields of syndrome bits; decoding the syndrome bits to identify bits in the field of uncorrected bits that are in error; indicating non-correctable errors if two bits in the field of uncorrected bits are in error; generating a correction bit to correct a bit in error; and combining the field of uncorrected bits with the correction bit to generate a field of corrected bits. 15. A method of operating a multistate memory cell, the cell having one of 8 states, the method comprising:reading the cell to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 12 percent of X volts, or between approximately 12.2 percent and 24 percent of X volts, or between approximately 24.2 percent and 36 percent of X volts, or between approximately 36.2 percent and 48 percent of X volts, or between approximately 48.2 percent and 60 percent of X volts, or between approximately 60.2 percent and 72 percent of X volts, or between approximately 72.2 percent and 84 percent of X volts, or between approximately 84.2 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; encoding the voltage signal into one of a sequence of encoded signals E1, E2, E3, E4, E5, E6, E7, and E8, each of the encoded signals representing a unique ordered set of binary bits and adjacent ones of the encoded signals being different in only a single bit; and performing error detection and correction on the encoded signal to detect errors in the encoded signal and to correct correctable errors in the encoded signal. 16. The method of claim 15 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the encoded signals E1, E2, E3, E4, E5, E6, E7, and E8 represent, respectively, 000, 001, 011, 010, 110, 111, 101, and 100 or 000, 100, 001, 001, 011, 111, 110, and 010; reading the cell further comprises: selecting the cell from a plurality of multistate flash memory cells in an array; sensing a current in the cell indicative of the state of the cell that is represented by a charge stored on a floating gate of the cell; and converting the current into the voltage signal; encoding the voltage signal further comprises: comparing the voltage signal with a plurality of reference voltages to generate a plurality of reference signals; and converting the reference signals into the encoded signal; and performing error detection and correction comprises: decoding the encoded signal and other encoded signals to generate a field of uncorrected bits and fields of syndrome bits; decoding the syndrome bits to identify bits in the field of uncorrected bits that are in error; indicating non-correctable errors if two bits in the field of uncorrected bits are in error; generating a correction bit to correct a bit in error; and combining the field of uncorrected bits with the correction bit to generate a field of corrected bits. 17. A method of operating a multistate memory cell, the cell having one of 8 states, the method comprising:reading the cell to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 12 percent of X volts, or between approximately 12.2 percent and 24 percent of X volts, or between approximately 24.2 percent and 36 percent of X volts, or between approximately 36.2 percent and 48 percent of X volts, or between approximately 48.2 percent and 60 percent of X volts, or between approximately 60.2 percent and 72 percent of X volts, or between approximately 72.2 percent and 84 percent of X volts, or between approximately 84.2 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; converting the voltage signal into a field of bits; and performing error detection and correction on the field of bits to detect errors in the field of bits and to correct correctable errors in the field of bits. 18. The method of claim 17 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; reading the cell further comprises: selecting the cell from a plurality of multistate flash memory cells in an array; sensing a current in the cell indicative of the state of the cell that is represented by a charge stored on a floating gate of the cell; and converting the current into the voltage signal; converting the voltage signal further comprises: comparing the voltage signal with a plurality of reference voltages to generate a plurality of reference signals; and converting the reference signals into the field of bits; and performing error detection and correction comprises: decoding the field of bits and other fields of bits to generate a field of uncorrected bits and fields of syndrome bits; decoding the syndrome bits to identify bits in the field of uncorrected bits that are in error; indicating non-correctable errors if two bits in the field of uncorrected bits are in error; generating a correction bit to correct a bit in error; and combining the field of uncorrected bits with the correction bit to generate a field of corrected bits. 19. A memory system comprising:an array of memory cells wherein each of the cells has one of 8 states; a read circuit coupled to the array to read one of the cells and to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 12 percent of X volts, or between approximately 12.2 percent and 24 percent of X volts, or between approximately 24.2 percent and 36 percent of X volts, or between approximately 36.2 percent and 48 percent of X volts, or between approximately 48.2 percent and 60 percent of X volts, or between approximately 60.2 percent and 72 percent of X volts, or between approximately 72.2 percent and 84 percent of X volts, or between approximately 84.2 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; an encoding circuit coupled to the read circuit to encode the voltage signal into one of a sequence of encoded signals E1, E2, E3, E4, E5, E6, E7, and E8, each of the encoded signals representing a unique ordered set of binary bits; and an error detection and correction circuit coupled to the encoding circuit to detect errors in the encoded signal and to correct correctable errors in the encoded signal. 20. The memory system of claims wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the encoded signals E1, E2, E3, E4, E5, E6, E7, and E8, represent, respectively, 000, 001, 011, 010, 110, 111, 101, and 100 or 000, 100, 101, 001, 011, 111, 110, and 010; the memory system comprises an integrated circuit memory system; each of the cells comprises a multistate flash memory cell; the read circuit comprises a sense amplifier circuit to convert a current in the cell into the voltage signal; the encoding circuit comprises: a plurality of comparator circuAs, each comparator circuit coupled between the sense amplifier circuit and a reference voltage to receive the voltage signal and to compare the voltage signal with the reference voltage to generate a reference signal; and a logic circuit coupled to receive the reference signals and to generate the encoded signal; the error detection and correction circuit comprises: an ECC decoder circuit coupled to the logic circuit to receive the encoded signal and other encoded signals, to assert the encoded signal representing data bits, and to generate syndrome bits from the other encoded signals representing ECC check bits; a syndrome decoder circuit coupled to receive and decode the syndrome bits, to generate correction bits based on the syndrome bits, and to assert a failure signal if the syndrome bits indicate an error in more than one of the data bits represented by the encoded signal; and a correction circuit coupled to receive the data bits represented by the encoded signal and the correction bits, to replace one of the data bits that is in error based on the correction bits, and to generate corrected bits. 21. A memory system comprising:an array of memory cells wherein each of the cells has one of 8 states; a read circuit coupled to the array to read one of the cells and to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 12 percent of X volts, or between approximately 12.2 percent and 24 percent of X volts, or between approximately 24.2 percent and 36 percent of X volts, or between approximately 36.2 percent and 48 percent of X volts, or between approximately 48.2 percent and 60 percent of X volts, or between approximately 60.2 percent and 72 percent of X volts, or between approximately 72.2 percent and 84 percent of X volts, or between approximately 84.2 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; an encoding circuit coupled to the read circuit to encode the voltage signal into one of a sequence of encoded signals E1, E2, E3, E4, E5, E6, E7, and E8, each of the encoded signals representing a unique ordered set of binary bits and adjacent ones of the encoded signals being different in only a single bit; and an error detection and correction circuA coupled to the encoding circuit to detect errors in the encoded signal and to correct correctable errors in the encoded signal. 22. The memory system of claim 21 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the encoded signals E1, E2, E3, E4, E5, E6, E7, and E8, represent, respectively, 000, 001, 011, 010, 110, 111, 101, and 100 or 000, 100, 101, 001, 011, 111, 110, and 010; the memory system comprises an integrated circuit memory system; each of the cells comprises a multistate flash memory cell; the read circuit comprises a sense amplifier circuit to convert a current in the cell into the voltage signal; the encoding circuit comprises: a plurality of comparator circuits, each comparator circuit coupled between the sense amplifier circuit and a reference voltage to receive the voltage signal and to compare the voltage signal with the reference voltage to generate a reference signal; and a logic circuit coupled to receive the reference signals and to generate the encoded signal; the error detection and correction circuit comprises: an ECC decoder circuit coupled to the logic circuit to receive the encoded signal and other encoded signals, to assert the encoded signal representing data bits, and to generate syndrome bits from the other encoded signals representing ECC check bits; a syndrome decoder circuit coupled to receive and decode the syndrome bits, to generate correction bits based on the syndrome bits, and to assert a failure signal if the syndrome bits indicate an error in more than one of the data bits represented by the encoded signal; and a correction circuit coupled to receive the data bits represented by the encoded signal and the correction bits, to replace one of the data bits that is in error based on the correction bits, and to generate corrected bits. 23. A memory system comprising:an array of memory cells wherein each of the cells has one of 8 states; a read circuit coupled to the array to read one of the cells and to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 12 percent of X volts, or between approximately 12.2 percent and 24 percent of X volts, or between approximately 24.2 percent and 36 percent of X volts, or between approximately 36.2 percent and 48 percent of X volts, or between approximately 48.2 percent and 60 percent of X volts, or between approximately 60.2 percent and 72 percent of X volts, or between approximately 72.2 percent and 84 percent of X volts, or between approximately 84.2 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; an encoding circuit coupled to the read circuit to encode the voltage signal into a field of bits; and an error detection and correction circuit coupled to the encoding circuit to detect errors in the field of bits and to correct correctable errors in the field of bits. 24. The memory system of claim 23 wherein:the minimum voltage comprises 0 volts and X volts comprises 5 volts; the memory system comprises an integrated circuit memory system; each of the cells comprises a multistate flash memory cell; the read circuit comprises a sense amplifier circuit to convert a current in the cell into the voltage signal; the encoding circuit comprises: a plurality of comparator circuits, each comparator circuit coupled between the sense amplifier circuit and a reference voltage to receive the voltage signal and to compare the voltage signal with the reference voltage to generate a reference signal; and a logic circuit coupled to receive the reference signals and to generate the field of bits; the error detection and correction circuit comprises: an ECC decoder circuit coupled to the logic circuit to receive the field of bits and other fields of bits, to assert bits from the field of bits representing data bits, and to generate syndrome bits from bits from the other fields of bits representing ECC check bits; a syndrome decoder circuit coupled to receive and decode the syndrome bits, to generate correction bits based on the syndrome bits, and to assert a failure signal if the syndrome bits indicate an error in more than one of the bits from the field of bits representing data bits; and a correction circuit coupled to receive the bits representing data bits and the correction bits, to replace a bit that is in error based on the correction bits, and to generate corrected bits. 25. A memory device comprising:an array of memory cells wherein each of the cells has one of a plurality of states; a read circuit coupled to the array to read one of the cells and to generate a voltage signal indicative of the state of the cell, the voltage signal being between approximately 0 percent and 24 percent of X volts, or between approximately 25 percent and 49 percent of X volts, or between approximately 50 percent and 74 percent of X volts, or between approximately 75 percent and 100 percent of X volts, wherein X volts comprises a selected voltage defined from a minimum voltage; means for encoding the voltage signal into a field of bits representing the state of the cell; and means for detecting and correcting a single erroneous bit in the field of bits and for asserting a failure signal upon detecting more than one erroneous bit in the field of bits. 26. A method of operating a 4-state memory cell, comprising:generating a voltage signal indicative of the state of the cell, wherein generating the voltage signal includes one from the group of generating the voltage signal between approximately 0 percent and 24 percent of X volts based on reading a first state, generating the voltage signal between approximately 25 percent and 49 percent of X volts based on reading a second state, generating the voltage signal between approximately 50 percent and 74 percent of X volts based on reading a third state, and generating the voltage signal between approximately 75 percent and 100 percent of X volts based on reading a fourth state, wherein X volts comprises a selected voltage defined above a minimum voltage; encoding the voltage signal into one of a sequence of encoded signals E1, E2, E3, and E4, each of the encoded signals representing a unique ordered set of binary bits; and performing error detection and correction on the encoded signal to detect errors in the encoded signal and to correct correctable errors in the encoded signal.