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Mixed hardware/software architecture and method for processing xDSL communications

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-01750
  • G06F-00900
  • G06F-01900
  • G06F-01500
출원번호 US-0797793 (2001-03-01)
발명자 / 주소
  • Liu, Ming-Kang
출원인 / 주소
  • Realtek Semiconductor Corp.
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett &
인용정보 피인용 횟수 : 14  인용 특허 : 42

초록

A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable

대표청구항

1. A method of implementing a scaleable architecture for a communications system based on minimizing a total gate count for the communications system, the method comprising the steps of:(a) dividing a communications transmission process into a set of N individual transmission tasks (T1, T2, . . . TN

이 특허에 인용된 특허 (42)

  1. Daniel Thomas ; Nattkemper Dieter ; Varma Subir, ATM communication system interconnect/termination unit.
  2. John C. Sinibaldi ; Himanshu Parikh ; Veerbhadra S. Kulkarni ; David A. Frye ; Gary L. Turbeville, Adaptive method and apparatus for allocation of DSP resources in a communication system.
  3. Bheda Hemant ; Gongalore Sanjay ; Srinivasan Partha, Apparatus and method for MPEG video decompression.
  4. Tomonaga Hiroshi (Kawasaki JPX) Matsuoka Naoki (Kawasaki JPX) Kawai Masaaki (Kawasaki JPX), Apparatus for high-speed packet switching in a broadband ISDN.
  5. Chang Web (39939 Stevenson Common ; V-2133 Fremont CA 94538), Application specific field programmable gate array.
  6. Gulick Dale ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system having a dedicated multimedia engine including multimedia memory.
  7. Sollars Donald L., Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations.
  8. Kadowaki Yukio,JPX, Digital signal processing device.
  9. Divine James ; Niehaus Jeffrey ; Dokic Miroslav ; Rao Raghunath ; Ritchie Terry ; Scott ; III Baker ; Pacourek John ; Luo Zheng, Dual processor digital audio decoder with shared memory data transfer and task partitioning for decompressing compressed audio data, and systems and methods using the same.
  10. Baxter Michael A., Dynamically reconfigurable computing using a processing unit having changeable internal hardware organization.
  11. Nasserbakht Mitra, Generalized fourier transform processing system.
  12. Mirfakhraei, Khashayar, Hybrid software/hardware discrete multi-tone transceiver.
  13. Furlong Darrell (Uxbridge MA), Local area network modem.
  14. Pechanek Gerald G. ; Kurak ; Jr. Charles W., Manifold array processor.
  15. Cummings Mark R., Method and apparatus for communicating information.
  16. Malladi Srinivasa R., Method and apparatus for designing re-usable core interface shells.
  17. Pechanek Gerald G. ; Pitsianis Nikos P. ; Barry Edwin F. ; Drabenstott Thomas L., Method and apparatus for manifold array processing.
  18. Marisetty Suresh K. ; Ravichandran Krishnan, Method and apparatus for sharing hardward resources in a computer system.
  19. Malladi Srinivasa R. ; Miller Marc A. ; Chau Kwok K., Method for partitioning hardware and firmware tasks in digital audio/video decoding.
  20. Hudson Michael ; Moore Daniel L., Method of configuring a functionally redefinable signal processing system.
  21. Pechanek Gerald G. ; Revilla Juan Guillermo ; Barry Edwin F., Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor.
  22. Pechanek Gerald G. ; Drabenstott Thomas L. ; Revilla Juan Guillermo ; Strube David Carl ; Morris Grayson, Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication.
  23. Barry Edwin F. ; Pechanek Gerald G. ; Drabenstott Thomas L. ; Wolff Edward A. ; Pitsianis Nikos P. ; Morris Grayson, Methods and apparatus for manarray PE-PE switch control.
  24. Reader Cliff ; Son Jae Cheol ; Qureshi Amjad ; Nguyen Le ; Frederiksen Mark ; Lu Tim, Methods and apparatus for processing video data.
  25. Pechanek Gerald G. ; Barry Edwin F. ; Revilla Juan Guillermo ; Larsen Larry D., Methods and apparatus for scalable instruction set architecture with dynamic compact instructions.
  26. Malladi Srinivasa R. ; Mattela Venkat, Micro architecture of video core for MPEG-2 decoder.
  27. Chung Jin-Chin (Hsinchu TX TWX) Wu Chuan-Lin (Austin TX), Multi-threaded microprocessor architecture utilizing static interleaving.
  28. Allsup Steven J. ; Dahlberg Bjorn M., Multiple function array based application specific integrated circuit.
  29. Fosmark Klaus S. ; Dibble Kevin S. ; Perry ; Jr. William A., Multiple mode xDSL interface.
  30. Kartalopoulos Stamatios V. (Clinton Township ; Hunterdon County NJ), Optimal parallel processor architecture for real time multitasking.
  31. Kan Takashi (Kanagawa JPX), Parallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system cont.
  32. Brown Glen W., Programmable data flow processor for performing data transfers.
  33. Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
  34. Hudson Michael ; Moore Daniel L., Redefinable signal processing subsystem.
  35. Cabrera Luis Felipe ; Dragoescu Claudia Beinglas, Scheduling computerized backup services.
  36. Vainsencher Leonardo, Single chip computer having integrated MPEG and graphical processors.
  37. Tran Jimmy Cuong ; Davidovici Sorin, Symbol-matched filter having a low silicon and power requirement.
  38. Baker Robert G. (Delray Beach FL) Eduartez Jose A. (Miami Beach FL) Huynh Duy Q. (Boca Raton FL) Swingle Paul R. (Delray Beach FL) Yong Suksoon (Boca Raton FL), System and method for efficiently loading and removing selected functions on digital signal processors without interrupt.
  39. Robinson Jeffrey I. (New Fairfield CT) Rouse Keith (New Milford CT) Krassowski Andrew J. (San Jose CA) Montlick Terry F. (Bethlehem CT), System for dividing processing tasks into signal processor and decision-making microprocessor interfacing therewith.
  40. Guezou Jean Adrien,FRX ; Ollivier Marcel,FRX ; Paris Bernard,FRX, System for interchanging data between data processor units having processors interconnected by a common bus.
  41. Luick David A. ; Winterfield Philip B., VLIW architecture and method for expanding a parcel.
  42. Luick David Arnold, Very long instruction word (VLIW) computer having efficient instruction code format.

이 특허를 인용한 특허 (14)

  1. Moore,Michael T.; Lie,James, Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD).
  2. Killian, Earl A.; Gonzalez, Ricardo E.; Dixit, Ashish B.; Lam, Monica; Lichtenstein, Walter D.; Rowen, Christopher; Ruttenberg, John C.; Wilson, Robert P.; Wang, Albert Ren-Rui; Maydan, Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
  3. Killian,Earl A.; Gonzalez,Ricardo E.; Dixit,Ashish B.; Lam,Monica; Lichtenstein,Walter D.; Rowen,Christopher; Ruttenberg,John C.; Wilson,Robert P.; Wang,Albert Ren Rui; Maydan,Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
  4. Hammes, Jeffrey, Efficiency of reconfigurable hardware.
  5. Culter,Bradley G., Firmware development within a framework from different design centers depositing component(s) with related contextual and genealogy information in an accessible repository.
  6. Deczky,Andrew, Method and system for DSL power saving.
  7. Schreiber,Robert S.; Gupta,Shail Aditya; Kathail,Vinod K.; Abraham,Santosh George; Rau,Bantwal Ramakrishna, Method and system for the design of pipelines of processors.
  8. Heise,Bernd, Method for transmitting data streams, and warm start sequence for S(H)DSL transmission/reception devices.
  9. Liu, Ming-Kang, Mixed hardware/software architecture and method for processing communications.
  10. Miyamoto, Carleton; Bandhole, Jagadish, Model for cost optimization and QoS tuning in hosted computing environments.
  11. Gupta,Shail Aditya; Sivaraman,Mukund, Pipeline stage initialization via task frame accessed by a memory pointer propagated among the pipeline stages.
  12. Kurimoto,Masahiro, Semiconductor integrated circuit using the same.
  13. Killian, Earl A.; Gonzalez, Ricardo E.; Dixit, Ashish B.; Lam, Monica; Lichtenstein, Walter D.; Rowen, Christopher; Ruttenberg, John C.; Wilson, Robert P.; Wang, Albert Ren-Rui; Maydan, Dror Eliezer, System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions.
  14. Killian, Earl A.; Gonzalez, Ricardo E.; Dixit, Ashish B.; Lam, Monica; Lichtenstein, Walter D.; Rowen, Christopher; Ruttenberg, John C.; Wilson, Robert P.; Wang, Albert Ren-Rui; Maydan, Dror Eliezer, System and method of designing instruction extensions to supplement an existing processor instruction set architecture.
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