IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0005135
(2001-11-30)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
3 인용 특허 :
25 |
초록
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A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module
A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.
대표청구항
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1. An apparatus for correcting programmatic time-gap defects in a computer system configured to communicate with devices of both synchronous and asynchronous types, the apparatus comprising:a processor configured to process data communicated with devices of both synchronous and asynchronous types; a
1. An apparatus for correcting programmatic time-gap defects in a computer system configured to communicate with devices of both synchronous and asynchronous types, the apparatus comprising:a processor configured to process data communicated with devices of both synchronous and asynchronous types; a controller comprising a buffer having a capacity of bytes and configured to temporarily store the data exchanged, the controller configured to control an exchange of data between the devices and to generate at least one content limiting interrupt corresponding to a near capacity condition of the buffer; and a memory device operably connected to the processor to store data comprising executables, the executables comprising: a driver configured to control operation of the controller, and an error avoidance module configured to be invoked by the driver upon generation of the at least one content limiting interrupt to monitor the transfer of bytes with respect to the buffer and to compare the capacity to a count of bytes transferred with respect to the buffer, and to force an error based on the comparison. 2. The apparatus of claim 1, wherein the error condition is forced if the value of the count corresponds to transfers of bytes causing exhaustion of buffer capacity.3. The apparatus of claim 1, wherein the driver further comprises an initialization module configured to enable executable data structures comprising the error avoidance module.4. The apparatus of claim 3, wherein the initialization module is further configured to enable a content limiting interrupt configured to occur when the content of the buffer approaches a capacity limit.5. The apparatus of claim 4, wherein the content limiting interrupt is configured to trigger the execution of the error avoidance module.6. The apparatus of claim 5, wherein the error avoidance module is configured to detect one of a read and a write operation.7. The apparatus of claim 6, wherein the error avoidance module is configured to detect both a read and a write operation.8. The apparatus of claim 7, wherein the buffer is selected from the group consisting of a register, a FIFO, and a content-addressable memory.9. A method for correcting programmatic time-gap defects in a computer system configured to communicate with devices of both synchronous and asynchronous types, the method comprising:transferring bytes of data between a device and a buffer having a capacity; providing a count of the bytes; comparing the count to the capacity; forcing an error condition corresponding to an unsuccessful transfer based on the count; and dynamically creating a content limiting interrupt configured to occur when the content of the buffer approaches a capacity limit. 10. The method of claim 9, wherein the error condition is forced if the value of the count is at least as large as the capacity.11. The method of claim 9, wherein the capacity limit is a plurality of limits.12. The method of claim 11, wherein the capacity limit is selected from the group consisting of a high and a low limit.13. The method of claim 9, wherein the capacity limit is both high and low limits.14. The method of claim 9, wherein the content limiting interrupt is configured to trigger the error avoidance module to initialize the count.15. The method of claim 14, wherein the buffer is selected from the group consisting of a register, a FIFO, and a content-addressable memory.16. A method for correcting programmatic time-gap defects in a computer system configured to communicate with devices of both synchronous and asynchronous types, the method comprising:transferring bytes of data between a device and a buffer having a capacity; providing a count of the bytes; comparing the count to the capacity; and forcing an error condition corresponding to an unsuccessful transfer of at least one of the bytes after transferring the bytes based on the count if the value of the count is at least as large as the capacity of the buffer added to a value corresponding to bytes that have been transferred both into and out of the buffer during a transfer operation. 17. The method of claim 16, further comprising dynamically creating a content limiting interrupt configured to occur when the content of the buffer approaches a capacity limit.18. The method of claim 17, wherein the capacity limit is a plurality of limits.19. The method of claim 17, wherein the capacity limit is selected from the group consisting of a high and a low limit.20. The method of claim 17, wherein the capacity limit is both high and low limits.21. The method of claim 17, wherein the content limiting interrupt is configured to trigger the error avoidance module to initialize the count.22. The method of claim 21, wherein the buffer is selected from the group consisting of a register, a FIFO, and a content-addressable memory.23. An article including a computer readable medium configured to correct programmatic time-gap defects in a computer system having synchronous and asynchronous devices interconnected to one another, the article comprising:a controller driver comprising executable and operational data structures configured to control operation of a controller in the computer system; and an error avoidance module configured to count the number of bytes transferred with respect to a buffer used by the controller, during an exchange of data, and to force an error condition corresponding to a failed transfer based on the count. 24. The article of claim 23, wherein the controller driver further comprises an initialization module configured to modify executable data structures of the controller driver to enable the error avoidance module.25. An apparatus for correcting programmatic time-gap defects, the apparatus comprising:a processor configured to communicate with devices of both synchronous an asynchronous types; and a controller for controlling an exchange of data between the devices, the controller including a controller memory storing executable data structures for programmatically controlling the controller and a buffer, having a byte capacity; and a memory device configured to store executables comprising: a driver configured to control the controller and invoke an error avoidance module, the error avoidance module configured to compare the byte capacity to a count of bytes transferred with respect to the buffer, and to force an error condition based on the count, and an initialization module configured to modify the executable data structures of the controller memory to generate an interrupt, the driver configured to invoke the error avoidance module upon generation of the interrupt. 26. An apparatus for correcting programmatic time-gap defects in a computer system configured to communicate with devices of both synchronous and asynchronous types, the apparatus comprising:a processor configured to process data communicated with devices of both synchronous and asynchronous types; a controller comprising a buffer configured to temporarily store the data exchanged and having a write capacity and a read capacity, the controller configured to control an exchange of data between the devices and to generate at least one FIFO interrupt corresponding to at least one of a nearly full condition of the buffer and a nearly empty condition of the buffer; and a memory device operably connected to the processor to store data structures comprising executables, the executables comprising: a driver configured to control operation of the controller, and an error avoidance module, the error avoidance module configured to be invoked by the driver upon generation of a FIFO interrupt to monitor the transfer of bytes with respect to the buffer and to compare at least one of the read capacity to a count of bytes read from the buffer and the write capacity to a count of bytes written to the buffer, and to force and error condition based on the comparison. 27. The apparatus of claim 26, wherein the error condition forced corresponds to an unsuccessful read or write operation.28. The apparatus of claim 27, wherein the memory further comprises an initialization module configured to enable the FIFO interrupt.29. The apparatus of claim 27, wherein the initialization module is further configured to reconfigure the driver to execute the error avoidance module upon generation of the FIFO interrupt.
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