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A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields. The first processor executes a single acquisition instruction to concurrently acquire a plurality of promotion bi

A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields. The first processor executes a single acquisition instruction to concurrently acquire a plurality of promotion bit fields exclusive of at least the second processor. In response to execution of the acquisition instruction, the first processor receives an indication of success or failure of the acquisition instruction, wherein the indication indicates success of the acquisition instruction if all of the plurality of promotion bit fields were concurrently acquired by the first processor and indicates failure of the acquisition instruction if fewer than all of the plurality of promotion bit fields were acquired by the first processor.

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1. A method of data processing within a multiprocessor data processing system including a plurality of processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields, said method comprising:a first processor among the plurality of processors e

1. A method of data processing within a multiprocessor data processing system including a plurality of processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields, said method comprising:a first processor among the plurality of processors executing a single acquisition instruction to concurrently acquire all of said plurality of promotion bit fields exclusive of at least a second processor among said plurality of processors; and in response to execution of said acquisition instruction, receiving within said first processor an indication of success or failure of said acquisition instruction, wherein said indication indicates success of said acquisition instruction if all of said plurality of promotion bit fields were concurrently acquired by said first processor and indicates failure of said acquisition instruction if fewer than all of said plurality of promotion bit fields were acquired by said first processor. 2. The method of claim 1, said processor including a register containing a register bit field, wherein said receiving comprises receiving said indication within a register bit field of said processor.3. The method of claim 1, and further comprising failing to acquire any of said plurality of promotion bit fields through execution of said acquisition instruction if all of said plurality of promotion bit fields are not concurrently acquired through execution of said acquisition instruction.4. The method of claim 1, and further comprising:in response to said indication indicating failure of said acquisition instruction, again executing said acquisition instruction. 5. The method of claim 1, wherein:said plurality of promotion bit fields are employed as locks; and executing said acquisition instruction comprises executing a lock acquisition instruction. 6. The method of claim 1, wherein:said plurality of promotion bit fields comprises a first plurality of promotion bit fields; said global promotion facility includes a second plurality of promotion bit fields; said method further comprises specifying said first plurality of promotion bit fields within one or more operands of said acquisition instruction. 7. The method of claim 1, and further comprising:in response to said execution of said single acquisition instruction, changing states of all of said plurality of promotion bit fields in said global promotion facility. 8. A processing unit for a data processing system having a global promotion facility and a plurality of processing units coupled by an interconnect, said processing unit comprising:an instruction sequencing unit; an execution unit coupled to the instruction sequencing unit, wherein said execution unit, responsive to a single acquisition instruction specifying a plurality of promotion bit fields within said global promotion facility, causes the processing unit to issue an access request to access to concurrently acquire all of said plurality of promotion bit fields exclusive of at least one other processing unit among said plurality of processing units; and a register including a register bit field indicating success or failure of said acquisition instruction, wherein said register bit field indicates success of said acquisition instruction if all of said plurality of promotion bit fields were concurrently acquired by said processing unit and indicates failure of said acquisition instruction if fewer than all of said plurality of promotion bit fields were acquired by said processing unit. 9. The processing unit of claim 8, wherein said register bit field further indicates failure of said processing unit to acquire any of said plurality of promotion bit fields through execution of said acquisition instruction if all of said plurality of promotion bit fields are not concurrently acquired through execution of said acquisition instruction.10. The processing unit of claim 8, wherein said instruction sequencing unit causes said execution unit to again execute said acquisition instruction in response to said indication indicating failure of said acquisition instruction.11. The processing unit of claim 8, wherein:said plurality of promotion bit fields are employed as locks; and said acquisition instruction comprises a lock acquisition instruction. 12. The processing unit of claim 8, wherein:said plurality of promotion bit fields comprises a first plurality of promotion bit fields; said global promotion facility includes a second plurality of promotion bit fields; and said acquisition instruction includes one or more operands specifying said first plurality of promotion bit fields. 13. A data processing system, comprising:a global promotion facility containing a promotion bit field; an interconnect; a plurality of processing units coupled to said global promotion facility and to the interconnect, wherein said plurality of processing units includes a second processing unit and a first processing unit, said first processing unit comprising: an instruction sequencing unit; an execution unit coupled to the instruction sequencing unit, wherein said execution unit, responsive to a single acquisition instruction specifying a plurality of promotion bit fields within said global promotion facility, causes the first processing unit to issue an access request to concurrently acquire all of said plurality of promotion bit fields exclusive of at said second processing unit; and a register including a register bit field indicating success or failure of said acquisition instruction, wherein said register bit field indicates success of said acquisition instruction if all of said plurality of promotion bit fields were concurrently acquired by said first processing unit and indicates failure of said acquisition instruction if fewer than all of said plurality of promotion bit fields were acquired by said first processing unit. 14. The data processing system of claim 13, wherein said register bit field further indicates failure of said processing unit to acquire any of said plurality of promotion bit fields through execution of said acquisition instruction if all of said plurality of promotion bit fields are not concurrently acquired through execution of said acquisition instruction.15. The data processing system of claim 13, wherein said instruction sequencing unit causes said execution unit to again execute said acquisition instruction in response to said indication indicating failure of said acquisition instruction.16. The data processing system of claim 13, wherein:said plurality of promotion bit fields are employed as locks; and said acquisition instruction comprises a lock acquisition instruction. 17. The data processing system of claim 13, wherein:said plurality of promotion bit fields comprises a first plurality of promotion bit fields; said global promotion facility includes a second plurality of promotion bit fields; and said acquisition instruction includes one or more operands specifying said first plurality of promotion bit fields. 18. The data processing system of claim 13, said global promotion facility having an associated controller that, responsive to said execution of said single acquisition instruction, changes states of all of said plurality of promotion bit fields in said global promotion facility.