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Semiconductor device having a bond pad and method therefor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-02940
출원번호 US-0097036 (2002-03-13)
발명자 / 주소
  • Yong, Lois E.
  • Harper, Peter R.
  • Tran, Tu Anh
  • Metz, Jeffrey W.
  • Leal, George R.
  • Dinh, Dieu Van
출원인 / 주소
  • Freescale Semiconductor, Inc.
인용정보 피인용 횟수 : 75  인용 특허 : 9

초록

A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal la

대표청구항

1. An integrated circuit comprising:a substrate having active circuitry and a perimeter; a plurality of layers of interconnect over the substrate; a final layer of interconnect over the plurality of layers of interconnect having a final layer pad and a plurality of interconnect lines, the final laye

이 특허에 인용된 특허 (9)

  1. Hubacher Eric M. (Austin TX), Bumped semiconductor device and method for probing the same.
  2. James Dennis B. (Rumson NJ) Moffitt Bryan S. (Red Bank NJ) Smith Douglas C. (Rumson NJ), Distributed time division multiplexing bus.
  3. Countryman Roger (Austin TX) Gerosa Gianfranco (Austin TX) Mendez Horacio (Austin TX), Electrostatic discharge protection device.
  4. Paul Davis Bell, Integrated circuit having wirebond pads suitable for probing.
  5. Shen Chi-Cheong ; Abbott Donald C. ; Bucksch Walter,DEX ; Corsi Marco ; Efland Taylor Rice ; Erdeljac John P. ; Hutter Louis Nicholas ; Mai Quang ; Wagensohner Konrad,DEX ; Williams Charles Edward, Integrated circuit with bonding layer over active circuitry.
  6. Chen Sheng-Hsiung,TWX, Integration process for Al pad.
  7. Stuart E. Greer, Method of forming copper interconnection utilizing aluminum capping film.
  8. Puar Deepraj S. (Sunnyvale CA), Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad.
  9. Saran Mukul, System and method for bonding over active integrated circuits.

이 특허를 인용한 특허 (75)

  1. Yu, Chen-Hua; Tseng, Horng-Huei, Bonding structure and fabrication thereof.
  2. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  3. Lin, Mou-Shiung, Chip package and method for fabricating the same.
  4. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  5. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  6. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  7. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  8. Kuo,Nick; Chou,Chiu Ming; Chou,Chien Kang; Lin,Chu Fu, Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto.
  9. Kwon, Heungkyu; Kim, Inhyuk, Chip using triple pad configuration and packaging method thereof.
  10. Pagani, Alberto, Circuit architecture for the parallel supplying during electric or electromagnetic testing of a plurality of electronic devices integrated on a semiconductor wafer.
  11. Wang, Mill-Jer; Peng, Ching-Nen; Lin, Hung-Chih; Chen, Hao, Circuit probing structures and methods for probing the same.
  12. Wang, Mill-Jer; Peng, Ching-Nen; Lin, Hung-Chih; Chen, Hao, Circuit probing structures and methods for probing the same.
  13. Mimura,Tadaaki; Hamatani,Tsuyoshi; Mizutani,Atuhito; Ueda,Kenji, Electrode pad section for external connection.
  14. Pagani, Alberto, Electronic devices with extended metallization layer on a passivation layer.
  15. Long,Jon M.; Foerstel,Joseph W., Elongated bonding pad for wire bonding and sort probing.
  16. Ryan,Vivian, Integrated circuit having bond pad with improved thermal and mechanical properties.
  17. Vo, Nhat D.; Tran, Tu-Anh N.; Carpenter, Burton J.; Hong, Dae Y.; Miller, James W.; Phillips, Kendall D., Integrated circuit having pads and input/output (I/O) cells.
  18. Tran, Tu-Anh; Eguchi, Richard K.; Harper, Peter R.; Lee, Chu-Chung; Williams, William M.; Yong, Lois, Integrated circuit with test pad structure and method of testing.
  19. Akiba, Toshihiko; Yasumura, Bunji; Sato, Masanao; Abe, Hiromi, Manufacturing method of semiconductor device.
  20. Rashid, Mohammed K.; Rashed, Mahbub M.; Roth, Scott S., Method of stimulating die circuitry and structure therefor.
  21. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  22. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  23. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  24. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  25. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  26. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  27. Pagani, Alberto, Method to perform electrical testing and assembly of electronic devices.
  28. Tran, Tu-Anh N.; Junker, Kurt H., Methods for forming semiconductor devices with stepped bond pads.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  30. Chen, Hsien-Wei, Pad structure having a metalized region and a non-metalized region.
  31. Condorelli, Vincenzo; Feger, Claudius; Gotze, Kevin C.; Hadzic, Nihad; Knickerbocker, John U.; Sprogis, Edmund J., Physically highly secure multi-chip assembly.
  32. Condorelli,Vincenzo; Feger,Claudius; Gotze,Kevin C.; Hadzic,Nihad; Knickerbocker,John U.; Sprogis,Edmund J., Physically highly secure multi-chip assembly.
  33. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  34. Michimata, Shigetomi; Yanagisawa, Masayuki; Kuroyanagi, Kazumasa, Probe resistance measurement method and semiconductor device with pads for probe resistance measurement.
  35. Michimata, Shigetomi; Yanagisawa, Masayuki; Kuroyanagi, Kazumasa, Probe resistance measurement method and semiconductor device with pads for probe resistance measurement.
  36. Antol,Joze E.; Seitzer,Philip William; Chesire,Daniel Patrick; Mengel,Rafe Carl; Archer,Vance Dolvan; Gans,Thomas B.; Kook,Taeho; Merchant,Sailesh M., Reinforced bond pad for a semiconductor device.
  37. Antol,Joze E.; Seitzer,Philip William; Chesire,Daniel Patrick; Mengel,Rafe Carl; Archer,Vance Dolvan; Gans,Thomas B.; Kook,Taeho; Merchant,Sailesh M., Reinforced bond pad for a semiconductor device.
  38. Hata,William Y., Reticle for layout modification of wafer test structure areas.
  39. Hata, William Y., Reticle for wafer test structure areas.
  40. Lam, Kan Wae; Horstink, Harrie Martinus Maria; Walczyk, Sven; Leung, Chi Ho; Jans, Thierry; Umali, Pompeo V.; Yeung, Shun Tik, Reversible semiconductor die.
  41. Archer, III, Vance D.; Ayukawa, Michael C.; Bachman, Mark A.; Chesire, Daniel P.; Kang, Seung H.; Kook, Taeho; Merchant, Sailesh M.; Steiner, Kurt G., Routing under bond pad for the replacement of an interconnect layer.
  42. Tsao,Pei Haw; Huang,Chender; Hou,Shang Yu; Su,Chao Yuan; Hsu,Chia Hsiung, Semiconductor bond pad structures and methods of manufacturing thereof.
  43. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  44. Akiba, Toshihiko; Yasumura, Bunji; Sato, Masanao; Abe, Hiromi, Semiconductor device.
  45. Akiba, Toshihiko; Yasumura, Bunji; Sato, Masanao; Abe, Hiromi, Semiconductor device.
  46. Takahashi, Masao; Takemura, Koji; Sakashita, Toshihiko; Mimura, Tadaaki, Semiconductor device.
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  48. Takahashi, Masao; Takemura, Koji; Sakashita, Toshihiko; Mimura, Tadaaki, Semiconductor device.
  49. Tanabe, Akihito, Semiconductor device and manufacturing method thereof.
  50. Yong,Lois E.; Harper,Peter R.; Tran,Tu Anh; Metz,Jeffrey W.; Leal,George R.; Van Dinh,Dieu, Semiconductor device having a bond pad and method therefor.
  51. Yang, Hyang-Ja, Semiconductor device including a metal layer having a first pattern and a second pattern which together form a web structure, thereby providing improved electrostatic discharge protection.
  52. Mun, Chear-yeon, Semiconductor device including bonding pads and semiconductor package including the semiconductor device.
  53. Akiba, Toshihiko; Yasumura, Bunji; Sato, Masanao; Abe, Hiromi, Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area.
  54. Akiba, Toshihiko; Yasumura, Bunji; Sato, Masanao; Abe, Hiromi, Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area.
  55. Pagani, Alberto; Ziglioli, Federico Giovanni, Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure.
  56. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  57. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  58. Mikalo, Ricardo, Staggered electrical frame structures for frame area reduction.
  59. Vollertsen, Rolf-Peter, Structured semiconductor element for reducing charging effects.
  60. Hata, William Y., Techniques for reticle layout to modify wafer test structure area.
  61. Low,Qwai H.; Ranganathan,Ramaswamy; Ali,Anwar; Lau,Tauman T., Test structure for detecting bonding-induced cracks.
  62. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  63. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  66. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  67. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  68. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  69. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  70. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  71. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  72. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  73. Chou, Chiu-Ming; Lin, Shih-Hsiung; Lin, Mou-Shiung; Lo, Hsin-Jung, Wire bonding method for preventing polymer cracking.
  74. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
  75. Murayama, Kei; Sunohara, Masahiro; Shiraishi, Akinori; Sakaguchi, Hideaki, Wiring substrate and semiconductor device.
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