IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0187236
(2002-06-28)
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발명자
/ 주소 |
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출원인 / 주소 |
- Lattice Semiconductor Corp.
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인용정보 |
피인용 횟수 :
1 인용 특허 :
13 |
초록
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A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used within a vector processing block (VPB) that operates on data in vector format. The PLD includes multipl
A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used within a vector processing block (VPB) that operates on data in vector format. The PLD includes multiple programmable logic blocks that are configurable by a user. The logic blocks operate on data at a bit level resulting in unordered bits of information in a PLD domain. However, a vector processing block operates on data on a vector level (e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc.). Thus, an interface is coupled between the programmable logic blocks and the vector processing block that converts at least a portion of the unordered bits of information from the PLD domain to one or more fixed-width vectors for use in the vector processing block. The interface may also perform scaling and/or sign extension on the unordered bits, to further free up expensive resources in the PLD domain.
대표청구항
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1. A programmable logic device (PLD), comprising:multiple programmable logic blocks that perform operations on a bit-by-bit basis in a PLD domain, such that the bits are unordered; an engine operable to process data, the engine performing operations on data ordered in vectors; and an interface coupl
1. A programmable logic device (PLD), comprising:multiple programmable logic blocks that perform operations on a bit-by-bit basis in a PLD domain, such that the bits are unordered; an engine operable to process data, the engine performing operations on data ordered in vectors; and an interface coupled between a programmable logic block and the engine, the interface operable to convert at least a portion of the unordered bits from the PLD domain to a vector and providing the vector to the engine, wherein the interface is operable to perform sign extension on the unordered bits in the conversion of the unordered bits to a vector. 2. A programmable logic device (PLD), comprising:multiple programmable logic blocks that perform operations on a bit-by-bit basis in a PLD domain, such that the bits are unordered; an engine operable to process data, the engine performing operations on data ordered in vectors; and an interface coupled between a programmable logic block and the engine, the interface operable to convert at least a portion of the unordered bits from the PLD domain to a vector and providing the vector to the engine, wherein the interface includes two stages, a first stage having multiple fuses configured to select unordered bits, which are used in part to create a fixed-width vector, and a second stage configured to perform the conversion of the selected unordered bits into the fixed-width vector. 3. The circuit of claim 2, wherein the second stage includes power and ground conductors having multiple fuses coupled thereto for selectively programming constants into the fixed-width vector and combining the constants with the selected unordered bits to create the fixed-width vector.4. The circuit of claim 2, wherein the first stage includes an input port having a first set of conductors configured to carry signals associated with the unordered bits and a second set of conductors perpendicular to the first set of conductors forming potential interconnection points between the first and second set of conductors.5. The circuit of claim 4, further including an array of fuses positioned at the potential interconnection points to allow selective programming of the first stage, each fuse being programmable to directly connect one of the first set of conductors to one of the second set of conductors.6. A programmable logic device (PLD), comprising:multiple programmable logic blocks that perform operations on a bit-by-bit basis in a PLD domain, such that the bits are unordered; an engine operable to process data, the engine performing operations on data ordered in vectors; and an interface coupled between a programmable logic block and the engine, the interface operable to convert at least a portion of the unordered bits from the PLD domain to a vector and providing the vector to the engine, wherein the interface includes a first stage and a second stage and a set of parallel conductors extending from the first stage into the second stage, the second stage including multiple fuses coupled to the parallel conductors for selectively programming which signals on the parallel conductors are used by the second stage. 7. A programmable logic device (PLD), comprising:multiple programmable logic blocks that perform operations on a bit-by-bit basis in a PLD domain, such that the bits are unordered; an engine operable to process data, the engine performing operations on data ordered in vectors; and an interface coupled between a programmable logic block and the engine, the interface operable to convert at least a portion of the unordered bits from the PLD domain to a vector and providing the vector to the engine, wherein the interface allows for selecting a same unordered bit multiple times in forming a single vector. 8. An interface within a PLD, comprising:an input port coupled to unordered bits in a PLD domain; a first stage coupled to the input port, the first stage including a first array of programmable fuses and a first set of multiple parallel signal conductors, the fuses allowing programmable connection between selected unordered bits from the input port and selected ones of the multiple parallel signal conductors from the first set, and a second stage coupled to the first stage and having a second array of programmable fuses and a second set of multiple parallel signal conductors, the second array of programmable fuses allowing programmable connection between selected ones of the first set of multiple parallel signal conductors and the second set of multiple parallel signal conductors to receive the unordered bits from the first set of multiple parallel conductors and convert the bits into fixed-width vectors to use in a vector processing block. 9. The circuit of claim 8, wherein the first stage has an address section and a data section.10. The circuit of claim 8, wherein the second stage includes a third set of parallel conductors, and further including programmable fuses to selectively connect the third set of conductors to the second set of multiple parallel conductors.11. The circuit of claim 8, wherein the unordered bits from the PLD domain are scaled using the second stage.12. The circuit of claim 8, wherein at least a portion of the unordered bits from the PLD domain are scaled to a different magnitude in the second stage and converted into a fixed-width vector.13. The circuit of claim 8, wherein at least a portion of the unordered bits from the PLD domain are sign-extended to a predetermined vector length in the second stage and converted into a fixed-width vector.14. The circuit of claim 8, wherein conductors from the input port and the first set of multiple parallel signal conductors are perpendicular to each other with the fuses being positioned at selected points of intersection.15. The circuit of claim 8, wherein an unordered bit may be selected multiple times in the second stage to form a single vector.16. A method of converting unordered bits in a PLD domain to fixed-width vectors for use in a vector domain, comprising:receiving the unordered bits from the PLD domain; selecting which of the unordered bits to use in the vector domain; and converting the unordered bits into fixed-width vectors to use in the Vector domain. 17. The method of claim 16, wherein converting includes scaling the unordered bits using constants.18. The method of claim 16, wherein converting includes performing sign extension.19. The method of claim 16, wherein converting includes programmably connecting power and ground to some of the bits in a fixed-width vector and combining the power and ground connections with some of the unordered bits to create the fixed-width vector.20. A circuit for converting unordered bits in a PLD domain to fixed-width vectors for use in a vector domain, comprising:means for receiving the unordered bits from the PLD domain; means for selecting which of the unordered bits to use in the vector domain; and means for converting the unordered bits into fixed-width vectors. 21. The circuit of claim 20, wherein the selecting means includes means for programmably connecting the received unordered bits to the converting means.22. The circuit of claim 20, wherein the converting means includes means for scaling the unordered bits.23. The circuit of claim 20, wherein the converting means includes means for extending the sign of the unordered bits.24. A field programmable gate array (FPGA), comprising:an FPGA domain including multiple programmable logic blocks that process data in the form of individual bits; a vector domain including one or more engines that process data in the form of vectors that each include multiple bits; and an interface coupled between the FPGA domain and the vector domain, the interface operable to convert individual bits received from the FPGA domain into a vector for processing in the vector domain, wherein the interface is configurable to select individual bits received from the FPGA domain and to arrange the selected bits into a predetermined order in the vector. 25. The FPGA of claim 24 wherein interface is configurable to format the selected bits into a vector having a fixed bit width.26. The FPGA of claim 25 wherein the interface is configurable to shift the selected bits and/or extend the sign of the selected bits within a vector.27. A field programmable gate array (FPGA), comprising:an FPGA domain including multiple programmable logic blocks that process data in the form of individual bits; a vector domain including one or more engines that process data in the form of vectors that each include multiple bits; and an interface coupled between the FPGA domain and the vector domain, the interface operable to convert individual bits received from the FPGA domain into a vector for processing in the vector domain, wherein the interface comprises: a first stage configurable to select individual bits from the FPGA domain; and a second stage configurable to arrange the selected bits into a predetermined order in the vector. 28. The FPGA of claim 27 wherein the second stage is configurable to format the selected bits into a vector having a fixed bit width.29. The FPGA of claim 28 wherein the second stage includes a first formatting circuit operable to shift the selected bits and/or a second formatting circuit operable to extend the sign of the selected bits.30. The FPGA of claim 28 wherein the second stage is configurable to convert the selected bits into a data vector and/or an address vector.31. The FPGA of claim 28 wherein the first stage comprises a partially populated switch matrix and the second stage comprises a fully populated switch matrix.32. An interface within an FPGA comprising:a first stage configurable to select individual bits from a set of bits produced by programmable logic blocks within the FPGA; and a second stage configurable to arrange and format the selected bits into a vector having a fixed bit width, the second stage including a first formatting circuit operable to shift the selected bits and/or a second formatting circuit operable to extend the sign of the selected bits.
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