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A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logic

A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

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1. A configurable logic element (CLE) for a programmable logic device (PLD), the CLE comprising:a plurality of data input terminals comprising first, second, and third sets of data input terminals; a programmable multiplexer having first and second sets of input terminals coupled respectively to the

1. A configurable logic element (CLE) for a programmable logic device (PLD), the CLE comprising:a plurality of data input terminals comprising first, second, and third sets of data input terminals; a programmable multiplexer having first and second sets of input terminals coupled respectively to the first and second sets of data input terminals, and further having output terminals; a read decoder having input terminals coupled to the third set of data input terminals and further having output terminals; a memory array having a plurality of input terminals coupled to the plurality of data input terminals, a plurality of address terminals coupled to the output terminals of the read decoder, and a plurality of output terminals; and an output multiplexer having a plurality of input terminals coupled to the output terminals of the memory array, a plurality of control terminals coupled to the output terminals of the programmable multiplexer, and a first output terminal. 2. The CLE of claim 1, wherein the memory array comprises rows and columns of memory cells, the CLE further comprising:a plurality of AND structures, each AND structure being coupled to the memory cells in one of the columns of the memory array; and a plurality of product term output terminals each coupled to an output terminal of one of the AND structures. 3. The CLE of claim 1, wherein the output multiplexer comprises:a first multiplexer having a plurality of input terminals coupled to a first subset of the output terminals of the memory array, a plurality of control terminals coupled to the output terminals of the programmable multiplexer, and an output terminal coupled to the first output terminal of the output multiplexer; and a second multiplexer having a plurality of input terminals coupled to a second subset of the output terminals of the memory array, a plurality of control terminals coupled to the second set of data input terminals, and an output terminal coupled to a second output terminal of the output multiplexer. 4. The CLE of claim 3, further comprising:an AB expander having a first input terminal coupled to the output terminal of the first multiplexer, a second input terminal coupled to the output terminal of the second multiplexer, and an output terminal, the AB expander having at least two configurable functions one of which is a multiplexer function. 5. The CLE of claim 4, wherein the configurable functions of the AB expander include an OR function.6. The CLE of claim 1, wherein the plurality of data input terminals comprises eight input terminals.7. The CLE of claim 6, wherein the first and second sets of data input terminals each comprise three data input terminals, and the third set of data input terminals comprises two data input terminals.8. A configurable logic element (CLE) for a programmable logic device (PLD), the CLE comprising:a plurality of data input terminals comprising first, second, and third sets of data input terminals; a programmable multiplexer having first and second sets of input terminals coupled respectively to the first and second sets of data input terminals, and further having output terminals; a read decoder having input terminals coupled to the third set of data input terminals and further having output terminals; a first memory array having a plurality of input terminals coupled to a first subset of the data input terminals, a plurality of address terminals coupled to the output terminals of the read decoder, and a plurality of output terminals; a second memory array having a plurality of input terminals coupled to a second subset of the data input terminals, a plurality of address terminals coupled to the output terminals of the read decoder, and a plurality of output terminals; a first output multiplexer having a plurality of input terminals coupled to the output terminals of the first memory array, a plurality of control terminals coupled to the output terminals of the programmable multiplexer, and an output terminal; and a second output multiplexer having a plurality of input terminals coupled to the output terminals of the second memory array, a plurality of control terminals coupled to the second set of data input terminals, and an output terminal. 9. The CLE of claim 8, wherein the first and second memory arrays each comprise rows and columns of memory cells, the CLE further comprising:a plurality of AND structures, each AND structure being coupled to the memory cells in one of the columns of each of the first and second memory arrays; and a plurality of product term output terminals each coupled to an output terminal of one of the AND structures. 10. The CLE of claim 8, further comprising:an AB expander having a first input terminal coupled to the output terminal of the first output multiplexer, a second input terminal coupled to the output terminal of the second output multiplexer, and an output terminal, the AB expander having at least two configurable functions one of which is a multiplexer function. 11. The CLE of claim 10, wherein the configurable functions of the AB expander include an OR function.12. The CLE of claim 8, wherein the plurality of data input terminals comprises eight input terminals.13. The CLE of claim 12, wherein the first and second sets of data input terminals each comprise three data input terminals, and the third set of data input terminals comprises two data input terminals.