IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0376796
(2003-02-27)
|
우선권정보 |
DE-0010180 (2002-03-07) |
발명자
/ 주소 |
- Hsu, Sheng Teng
- Pan, Wei
- Zhuang, Wei-Wei
- Zhang, Fengyan
|
출원인 / 주소 |
- Sharp Laboratories of America, Inc.
|
인용정보 |
피인용 횟수 :
8 인용 특허 :
2 |
초록
▼
A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overl
A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls, and the method further comprises: forming an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.
대표청구항
▼
1. A method for fabricating a one-resistor/one-diode (1R1D) R-RAM array with a floating p-well, the method comprising:forming an integrated circuit (IC) substrate; forming an n-doped buried layer of silicon (buried n layer) overlying the substrate; forming a p-doped well of silicon (p-well) overlyin
1. A method for fabricating a one-resistor/one-diode (1R1D) R-RAM array with a floating p-well, the method comprising:forming an integrated circuit (IC) substrate; forming an n-doped buried layer of silicon (buried n layer) overlying the substrate; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. 2. The method of claim 1 further comprising:forming n-doped silicon sidewalls overlying the buried n layer; forming an n-doped well (n-well) of silicon from the combination of n-doped silicon sidewalls and the buried n layer; and, wherein forming a p-doped well of silicon (p-well) overlying the buried n layer includes forming the p-well inside th n-well. 3. The method of claim 2 wherein forming a p-well includes forming a p-well with sidewalk; and,the method further comprising: forming an oxide insulator overlying the p-well sidewalk, between the n-well and the R-RAM array. 4. The method of claim 3 wherein forming a p-well includes forming a p-well with a top surface; and,wherein forming a 1R1D R-RAM array overlying the p-well includes: forming a bit lines overlying the p-well top surface; forming b word lines overlying and orthogonal to the bit lines; and, forming (b×a) one-resistor/one-diode (1R1) elements interposed between each bit line and each overlying word line. 5. The method of claim 4 wherein forming (b ×a) one-resistor/one-diode(1R1) elements interposed between each bit line and each overlying word line includes:forming b, oxide insulated word line trenches overlying and orthogonal to the bit lines; in each trench forming a layer of p-doped silicon overlying the bit lines; forming a layer of bottom electrode (BE) overlying the p-doped layer; and, forming a layer of memory resistor material overlying the bottom electrode; and, wherein forming b word lines overlying and orthogonal to the bit lines includes forming the word lines overlying the memory resistor layers. 6. The method of claim 5 wherein forming a p-doped well of silicon (p-well) includes doping the p-well with a doping density in the range between 1×1015/cm3 and 1×1017/cm3.7. The method of claim 5 wherein forming an n-doped buried layer of silicon (n layer) overlying the substrate includes doping the n-well using a material selected from the group including phosphorous, at an energy of 500 KeV to 2 MeV, and arsenic, at an energy of 1 MeV to 5 MeV, with a doping density in the range between 1×1016/cm3 and 1×1017/cm3.8. The method of claim 5 wherein forming a bit lines overlying the p-well top surface includes forming a bit lines of n-doped silicon overlying the p-well top surface.9. The method of claim 5 wherein forming b word lines overlying and orthogonal to the bit lines includes forming word lines of top electrode (TE).10. The method of claim 5 wherein forming a layer of memory resistor material overlying the bottom electrode includes using a memory resistor material selected from the group including Pr0.3Ca0.7MnO3 (PCMO), colossal magnetoresistance (CMR), and high temperature superconductivity (HTSC) materials.11. The method of claim 5 wherein forming a layer of bottom electrode overlying the p-doped layer includes forming the bottom electrode from a material selected from the group including Pt, Ir, and Pt/TiN/Ti.12. The method of claim 1 wherein forming a p-doped well of silicon (p-well) overlying the buried n layer includes forming a p-well with a thickness in the range of 0.2 to 0.8 microns.13. A one-resistor/one-diode (1R1) R-RAM with a floating p-well, the R-RAM comprising:an integrated circuit (IC) substrate; an n-doped buried layer of silicon (buried n layer) overlying the substrate; a p-doped well of silicon (p-well) overlying the buried n layer; and, a 1R1D R-RAM array overlying and inside the p-well. 14. The R-RAM array of claim 13 further comprising:n-doped silicon sidewalls overlying the buried n layer, wherein the combination of the n-doped silicon sidewalls and the buried n layer forms an n-well; and, wherein the p-well is formed inside the n-well. 15. The R-RAM array of claim 14 wherein the p-well has sidewalls; and,the R-RAM further comprising: an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array. 16. The R-RAM array of claim 15 wherein the p-well has a top surface; and,wherein the 1R1D R-RAM array includes: a bit lines overlying the p-well top surface; b word lines overlying and orthogonal to the bit lines; and, (b×a) one-resistor/one-diode (1R1) elements interposed between each bit line and each overlying word line. 17. The R-RAM array of claim 16 further comprising:b oxide insulated word line trenches overlying and orthogonal to the bit lines; wherein the 1R1D elements includes: in each word line trench, a layer of p-doped silicon overlying the bit lines; a layer of bottom electrode (BE) overlying the p-doped layer; and, a layer of memory resistor material overlying the bottom; and, wherein the b word lines overlie the memory resistor layers. 18. The R-RAM array of claim 17 wherein the p-well is doped with a doping density in the range between 1×1015/cm3 and 1×1017/cm3.19. The R-RAM array of claim 17 wherein the n-well is doped with a material selected from the group including phosphorous, at an energy of 500 KeV to 2 MeV, and arsenic, at an energy of 1 MeV to 5 MeV, with a doping density in the range between 1×1016/cm3 and 1×1017/cm3.20. The R-RAM array of claim 17 wherein the a bit lines are n-doped silicon.21. The R-RAM array of claim 17 wherein the b word lines are top electrodes.22. The R-RAM of claim 17 wherein the memory resistor material is selected from the group including Pr0.3Ca0.7MnO3 (PCMO), colossal magnetoresistance (CMR), and high temperature superconductivity (HTSC) materials.23. The R-RAM of claim 17 wherein the bottom electrode is a material selected from the group including Pt, Ir, and Pt/TiN/Ti.24. The R-RAM of claim 13 wherein the p-doped well of silicon has a thickness in the range of 0.2 to 0.8 microns.25. A method for fabricating a one-resistor/one-diode (1R1D) R-RAM array with a floating p-well, the method comprisingforming an integrated circuit (IC) substrate; forming an n-doped buried layer of silicon (buried n layer) overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming an n-doped well (n-well) of silicon from the combination of n-doped silicon sidewalls and the buried n layer; forming a p-doped well of silicon (p-well), with sidewalls and a top surface, overlying the buried n layer, inside the n-well; forming an oxide insulator overlying the p-well sidewalls; and, forming a 1R1D R-RAM array overlying the p-well as follows; forming a bit lines overlying the p-well top surface; forming b word lines overlying and orthogonal to the bit lines; and, forming (b×a) one-resistor/one-diode (1R1D) elements interposed between each bit line and each overlying word line. 26. A one-resistor/one-diode (1R1) R-RAM with a floating p-well, the R-RAM comprising:an integrated circuit (IC) substrate; an n-doped buried layer of silicon (buried n layer) overlying the substrate; n-doped silicon sidewalls overlying the buried n layer, wherein the combination of the n-doped silicon sidewalls and the buried n layer forms an n-well; a p-doped well of silicon (p-well), with sidewalls and a top surface, overlying the buried n layer, inside the n-well; an oxide insulator overlying the p-well sidewalls; and, a 1R1D R-RAM array overlying and inside the p-well, wherein the 1R1D R-RAM array includes: a bit lines overlying the p-well top surface; b word lines overlying and orthogonal to the bit lines; and, (b×a) one-resistor/one-diode (1R1) elements interposed between each bit line and each overlying word line.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.